What are the types of shaft coupling to use on CNC ?

Coupling are used for transmitting torque between two shafts even when they are misaligned. For hobbyist CNCs they are used to connect the Stepper Motor axis and the leadscrew/ballscrew.

Rigid Coupling
The basic (and worst) coupling is the rigid couplings:

This coupling is good for transmitting torque between two shafts and has no backlash but doesn’t allow misalignment among shafts and will wear or damage the shafts very soon.

Oldham Coupling
The Oldham coupling has 3 discs (normally two metal discs and one plastic disc) and allow parallel shaft misalignment (offset) :

Oldham coupling can reduce the backlash, but there are better options as we will see next.

Jaw Coupling
As known as Spider Coupling or Lovejoy Coupling:

The Jaw coupling has 2 metal discs and an elastomer filling disc internally. They are good for torque transfer and damping support, but have some backlash.

Helical Coupling
As known as Beam coupling is a hollow cylinder with helical cut:

This coupling can support some degrees of misalignment and have low backlash.

Bellows coupling

Bellows coupling is a type of cylinder cut or electro-deposited to become a bellow:

This type of coupling allow misalignment and the lowest backlash of “flexibles couplings”.

Setting ASF to disable toolchain optimization

I hate to spend time trying to remember things that I already did in the past, but all times that I didn’t document it I always spend time figuring it out.

When compiling an ELF binary in the Atmel ASF studio I need to disable GCC optimization in order to get all debug info from GDB.

To disable Toolchain optimization in the ASF:

Project ->
        YourProjectName Properties... ->
                Toolchain ->
                        ARM/GNU C Compiler ->
                                Optimization ->
                                        Optimization Level = None (-O0)

Debug I2C SAML21 board initialization using GDB

You already saw how to use JLink to debug Atmel SAML21 microcontroller here.

Now we will see the GDB trace when debugging the I2C with callback sample:

$ arm-none-eabi-gdb i2c_int.elf
GNU gdb (7.6.50.20131218-0ubuntu1+1) 7.6.50.20131218-cvs

(gdb) target remote localhost:2331
Remote debugging using localhost:2331
0x00001de2 in ?? ()

(gdb) monitor reset
Resetting target

(gdb) load i2c_int.elf
Loading section .text, size 0x1334 lma 0x0
Loading section .relocate, size 0x8 lma 0x1334
Start address 0x1000, load size 4924
Transfer rate: 4808 KB/sec, 1641 bytes/write.

(gdb) b main
Breakpoint 1 at 0x1178: file ../src/qs_i2c_master_callback.c, line 130.

(gdb) c
Continuing.

Breakpoint 1, main () at ../src/qs_i2c_master_callback.c:130
130	{

(gdb) si
131		system_init();
(gdb) 
0x0000117c	131		system_init();
(gdb) 
system_init () at ../src/ASF/sam0/drivers/system/system.c:92
92	{
(gdb) 
94		system_clock_init();
(gdb) 
0x00000fdc	94		system_clock_init();
(gdb) 
system_clock_init () at ../src/ASF/sam0/drivers/system/clock/clock_saml21/clock.c:770
770	{
(gdb) 
0x00000ba6	770	{
(gdb) 
773		OSCCTRL->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY;
(gdb) 
0x00000baa	773		OSCCTRL->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY;
(gdb) 
0x00000bac	773		OSCCTRL->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY;
(gdb) 
0x00000bae	773		OSCCTRL->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY;
(gdb) 
774		SUPC->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY | SUPC_INTFLAG_BOD33DET;
(gdb) 
0x00000bb2	774		SUPC->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY | SUPC_INTFLAG_BOD33DET;
(gdb) 
0x00000bb4	774		SUPC->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY | SUPC_INTFLAG_BOD33DET;
(gdb) 
system_flash_set_waitstates (wait_states=0 '00')
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/clock_feature.h:1359
1359		NVMCTRL->CTRLB.bit.RWS = wait_states;
(gdb) 
0x00000bb8	1359		NVMCTRL->CTRLB.bit.RWS = wait_states;
(gdb) 
0x00000bba	1359		NVMCTRL->CTRLB.bit.RWS = wait_states;
(gdb) 
0x00000bbc	1359		NVMCTRL->CTRLB.bit.RWS = wait_states;
(gdb) 
0x00000bbe	1359		NVMCTRL->CTRLB.bit.RWS = wait_states;
(gdb) 
system_switch_performance_level (performance_level=SYSTEM_PERFORMANCE_LEVEL_2)
    at ../src/ASF/sam0/drivers/system/power/power_sam_l/power.h:741
741		if (performance_level == (enum system_performance_level)PM->PLCFG.reg) {
(gdb) 
0x00000bc2	741		if (performance_level == (enum system_performance_level)PM->PLCFG.reg) {
(gdb) 
0x00000bc4	741		if (performance_level == (enum system_performance_level)PM->PLCFG.reg) {
(gdb) 
0x00000bc6	741		if (performance_level == (enum system_performance_level)PM->PLCFG.reg) {
(gdb) 
0x00000bc8	741		if (performance_level == (enum system_performance_level)PM->PLCFG.reg) {
(gdb) 
system_cpu_clock_get_hz () at ../src/ASF/sam0/drivers/system/clock/clock_saml21/clock_feature.h:1021
1021		return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> (MCLK->CPUDIV.reg - 1));
(gdb) 
0x00000bcc	1021		return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> (MCLK->CPUDIV.reg - 1));
(gdb) 
0x00000bce	1021		return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> (MCLK->CPUDIV.reg - 1));
(gdb) 
system_gclk_gen_get_hz (generator=0 '00') at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:276
276	{
(gdb) 
0x00000df6	276	{
(gdb) 
system_gclk_is_syncing (generator=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:70
70		 if (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 <SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 <SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 <SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 <SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 <SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 << generator )){
(gdb) 
system_gclk_gen_get_hz (generator=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:277
277		while (system_gclk_is_syncing(generator)) {
(gdb) 
0x00000e06	277		while (system_gclk_is_syncing(generator)) {
(gdb) 
system_interrupt_enter_critical_section ()
    at ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:169
169		cpu_irq_enter_critical();
(gdb) 
0x00000e0a	169		cpu_irq_enter_critical();
(gdb) 
cpu_irq_enter_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:59
59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
0x00000116	59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
0x00000118	59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
0x0000011a	59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
__get_PRIMASK () at ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h:471
471	  __ASM volatile ("MRS %0, primask" : "=r" (result) );
(gdb) 
cpu_irq_enter_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:60
60			if (cpu_irq_is_enabled()) {
(gdb) 
0x00000122	60			if (cpu_irq_is_enabled()) {
(gdb) 
__disable_irq () at ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h:331
331	  __ASM volatile ("cpsid i");
(gdb) 
__DMB () at ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h:357
357	  __ASM volatile ("dmb");
(gdb) 
cpu_irq_enter_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:61
61				cpu_irq_disable();
(gdb) 
0x0000012c	61				cpu_irq_disable();
(gdb) 
0x0000012e	61				cpu_irq_disable();
(gdb) 
62				cpu_irq_prev_interrupt_state = true;
(gdb) 
0x00000132	62				cpu_irq_prev_interrupt_state = true;
(gdb) 
0x00000134	62				cpu_irq_prev_interrupt_state = true;
(gdb) 
0x00000136	62				cpu_irq_prev_interrupt_state = true;
(gdb) 
70		cpu_irq_critical_section_counter++;
(gdb) 
0x00000140	70		cpu_irq_critical_section_counter++;
(gdb) 
0x00000142	70		cpu_irq_critical_section_counter++;
(gdb) 
0x00000144	70		cpu_irq_critical_section_counter++;
(gdb) 
71	}
(gdb) 
system_gclk_gen_get_hz (generator=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:285
285				(enum system_clock_source)GCLK->GENCTRL[generator].bit.SRC);
(gdb) 
0x00000e0e	285				(enum system_clock_source)GCLK->GENCTRL[generator].bit.SRC);
(gdb) 
0x00000e10	285				(enum system_clock_source)GCLK->GENCTRL[generator].bit.SRC);
(gdb) 
0x00000e12	285				(enum system_clock_source)GCLK->GENCTRL[generator].bit.SRC);
(gdb) 
0x00000e14	285				(enum system_clock_source)GCLK->GENCTRL[generator].bit.SRC);
(gdb) 
0x00000e16	285				(enum system_clock_source)GCLK->GENCTRL[generator].bit.SRC);
(gdb) 
284		uint32_t gen_input_hz = system_clock_source_get_hz(
(gdb) 
0x00000e1a	284		uint32_t gen_input_hz = system_clock_source_get_hz(
(gdb) 
system_clock_source_get_hz (clock_source=SYSTEM_CLOCK_SOURCE_OSC16M)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/clock.c:198
198	{
(gdb) 
199		switch (clock_source) {
(gdb) 
0x00000b14	199		switch (clock_source) {
(gdb) 
0x00000b16	199		switch (clock_source) {
(gdb) 
0x00000b18	199		switch (clock_source) {
(gdb) 
0x00000b1a	199		switch (clock_source) {
(gdb) 
0x00000b1c	199		switch (clock_source) {
(gdb) 
204			return (OSCCTRL->OSC16MCTRL.bit.FSEL+1)*4000000UL;
(gdb) 
0x00000b2c	204			return (OSCCTRL->OSC16MCTRL.bit.FSEL+1)*4000000UL;
(gdb) 
0x00000b2e	204			return (OSCCTRL->OSC16MCTRL.bit.FSEL+1)*4000000UL;
(gdb) 
0x00000b30	204			return (OSCCTRL->OSC16MCTRL.bit.FSEL+1)*4000000UL;
(gdb) 
0x00000b32	204			return (OSCCTRL->OSC16MCTRL.bit.FSEL+1)*4000000UL;
(gdb) 
0x00000b34	204			return (OSCCTRL->OSC16MCTRL.bit.FSEL+1)*4000000UL;
(gdb) 
0x00000b36	204			return (OSCCTRL->OSC16MCTRL.bit.FSEL+1)*4000000UL;
(gdb) 
0x00000b38	204			return (OSCCTRL->OSC16MCTRL.bit.FSEL+1)*4000000UL;
(gdb) 
242	}
(gdb) 
0x00000e1c in system_gclk_gen_get_hz (generator=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:284
284		uint32_t gen_input_hz = system_clock_source_get_hz(
(gdb) 
287		uint8_t divsel = GCLK->GENCTRL[generator].bit.DIVSEL;
(gdb) 
0x00000e20	287		uint8_t divsel = GCLK->GENCTRL[generator].bit.DIVSEL;
(gdb) 
0x00000e22	287		uint8_t divsel = GCLK->GENCTRL[generator].bit.DIVSEL;
(gdb) 
288		uint32_t divider = GCLK->GENCTRL[generator].bit.DIV;
(gdb) 
0x00000e26	288		uint32_t divider = GCLK->GENCTRL[generator].bit.DIV;
(gdb) 
system_interrupt_leave_critical_section ()
    at ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:182
182		cpu_irq_leave_critical();
(gdb) 
0x00000e2a	182		cpu_irq_leave_critical();
(gdb) 
cpu_irq_leave_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:78
78		cpu_irq_critical_section_counter--;
(gdb) 
0x00000156	78		cpu_irq_critical_section_counter--;
(gdb) 
0x00000158	78		cpu_irq_critical_section_counter--;
(gdb) 
0x0000015a	78		cpu_irq_critical_section_counter--;
(gdb) 
82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x0000015e	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000160	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000162	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000164	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000166	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000168	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
83			cpu_irq_enable();
(gdb) 
0x0000016c	83			cpu_irq_enable();
(gdb) 
0x0000016e	83			cpu_irq_enable();
(gdb) 
__DMB () at ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h:357
357	  __ASM volatile ("dmb");
(gdb) 
__enable_irq () at ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h:320
320	  __ASM volatile ("cpsie i");
(gdb) 
cpu_irq_leave_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:85
85	}
(gdb) 
system_gclk_gen_get_hz (generator=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:293
293		if (!divsel && divider > 1) {
(gdb) 
0x00000e2e	293		if (!divsel && divider > 1) {
(gdb) 
0x00000e30	293		if (!divsel && divider > 1) {
(gdb) 
0x00000e32	293		if (!divsel && divider > 1) {
(gdb) 
300	}
(gdb) 
0x00000e46	300	}
(gdb) 
0x00000bd0 in system_cpu_clock_get_hz ()
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/clock_feature.h:1021
1021		return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> (MCLK->CPUDIV.reg - 1));
(gdb) 
0x00000bd2	1021		return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> (MCLK->CPUDIV.reg - 1));
(gdb) 
0x00000bd4	1021		return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> (MCLK->CPUDIV.reg - 1));
(gdb) 
0x00000bd6	1021		return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> (MCLK->CPUDIV.reg - 1));
(gdb) 
system_switch_performance_level (performance_level=SYSTEM_PERFORMANCE_LEVEL_2)
    at ../src/ASF/sam0/drivers/system/power/power_sam_l/power.h:745
745		if (system_cpu_clock_get_hz() >
(gdb) 
0x00000bda	745		if (system_cpu_clock_get_hz() >
(gdb) 
0x00000bdc	745		if (system_cpu_clock_get_hz() >
(gdb) 
751		PM->INTFLAG.reg = PM_INTFLAG_PLRDY;
(gdb) 
0x00000be0	751		PM->INTFLAG.reg = PM_INTFLAG_PLRDY;
(gdb) 
0x00000be2	751		PM->INTFLAG.reg = PM_INTFLAG_PLRDY;
(gdb) 
0x00000be4	751		PM->INTFLAG.reg = PM_INTFLAG_PLRDY;
(gdb) 
754		PM->PLCFG.reg = performance_level;
(gdb) 
0x00000be8	754		PM->PLCFG.reg = performance_level;
(gdb) 
757		while (!PM->INTFLAG.reg) {
(gdb) 
0x00000bec	757		while (!PM->INTFLAG.reg) {
(gdb) 
0x00000bee	757		while (!PM->INTFLAG.reg) {
(gdb) 
0x00000bf0	757		while (!PM->INTFLAG.reg) {
(gdb) 
system_clock_init () at ../src/ASF/sam0/drivers/system/clock/clock_saml21/clock.c:838
838			OSCCTRL->OSC16MCTRL.reg |= (CONF_CLOCK_OSC16M_ON_DEMAND <OSC16MCTRL.reg |= (CONF_CLOCK_OSC16M_ON_DEMAND <OSC16MCTRL.reg |= (CONF_CLOCK_OSC16M_ON_DEMAND <OSC16MCTRL.reg |= (CONF_CLOCK_OSC16M_ON_DEMAND <OSC16MCTRL.reg |= (CONF_CLOCK_OSC16M_ON_DEMAND <OSCULP32K.reg = (CONF_CLOCK_OSCULP32K_ENABLE_1KHZ_OUTPUT <OSCULP32K.reg = (CONF_CLOCK_OSCULP32K_ENABLE_1KHZ_OUTPUT <OSCULP32K.reg = (CONF_CLOCK_OSCULP32K_ENABLE_1KHZ_OUTPUT <APBAMASK.reg |= mask;
(gdb) 
0x00000cea	1116				MCLK->APBAMASK.reg |= mask;
(gdb) 
0x00000cec	1116				MCLK->APBAMASK.reg |= mask;
(gdb) 
0x00000cee	1116				MCLK->APBAMASK.reg |= mask;
(gdb) 
0x00000cf0	1116				MCLK->APBAMASK.reg |= mask;
(gdb) 
system_gclk_init () at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:90
90		GCLK->CTRLA.reg = GCLK_CTRLA_SWRST;
(gdb) 
0x00000cf4	90		GCLK->CTRLA.reg = GCLK_CTRLA_SWRST;
(gdb) 
0x00000cf6	90		GCLK->CTRLA.reg = GCLK_CTRLA_SWRST;
(gdb) 
91		while (GCLK->CTRLA.reg & GCLK_CTRLA_SWRST) {
(gdb) 
0x00000cfa	91		while (GCLK->CTRLA.reg & GCLK_CTRLA_SWRST) {
(gdb) 
0x00000cfc	91		while (GCLK->CTRLA.reg & GCLK_CTRLA_SWRST) {
(gdb) 
0x00000cfe	91		while (GCLK->CTRLA.reg & GCLK_CTRLA_SWRST) {
(gdb) 
94	}
(gdb) 
system_cpu_clock_set_divider (divider=SYSTEM_MAIN_CLOCK_DIV_1)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/clock_feature.h:976
976		MCLK->CPUDIV.reg = (uint32_t)divider;
(gdb) 
0x00000c08	976		MCLK->CPUDIV.reg = (uint32_t)divider;
(gdb) 
0x00000c0a	976		MCLK->CPUDIV.reg = (uint32_t)divider;
(gdb) 
system_main_clock_set_failure_detect (enable=false)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/clock_feature.h:961
961			MCLK->CTRLA.reg &= ~MCLK_CTRLA_CFDEN;
(gdb) 
0x00000c0e	961			MCLK->CTRLA.reg &= ~MCLK_CTRLA_CFDEN;
(gdb) 
0x00000c10	961			MCLK->CTRLA.reg &= ~MCLK_CTRLA_CFDEN;
(gdb) 
0x00000c12	961			MCLK->CTRLA.reg &= ~MCLK_CTRLA_CFDEN;
(gdb) 
system_low_power_clock_set_divider (divider=SYSTEM_MAIN_CLOCK_DIV_1)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/clock_feature.h:991
991		MCLK->LPDIV.reg = (uint32_t)divider;
(gdb) 
system_backup_clock_set_divider (divider=SYSTEM_MAIN_CLOCK_DIV_1)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/clock_feature.h:1006
1006		MCLK->BUPDIV.reg = (uint32_t)divider;
(gdb) 
system_gclk_gen_get_config_defaults (config=0x20002084) at ../src/ASF/sam0/drivers/system/clock/gclk.h:208
208		config->division_factor    = 1;
(gdb) 
0x00000c1a	208		config->division_factor    = 1;
(gdb) 
0x00000c1c	208		config->division_factor    = 1;
(gdb) 
209		config->high_when_disabled = false;
(gdb) 
211		config->source_clock       = GCLK_SOURCE_OSC16M;
(gdb) 
215		config->run_in_standby     = false;
(gdb) 
216		config->output_enable      = false;
(gdb) 
system_clock_init () at ../src/ASF/sam0/drivers/system/clock/clock_saml21/clock.c:1008
1008		_CONF_CLOCK_GCLK_CONFIG(0, ~);
(gdb) 
0x00000c28	1008		_CONF_CLOCK_GCLK_CONFIG(0, ~);
(gdb) 
0x00000c2a	1008		_CONF_CLOCK_GCLK_CONFIG(0, ~);
(gdb) 
system_gclk_gen_set_config (generator=0 '00', config=0x20002084)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:119
119	{
(gdb) 
0x00000d0e	119	{
(gdb) 
128		new_genctrl_config = config->source_clock <high_when_disabled) {
(gdb) 
0x00000d14	131		if (config->high_when_disabled) {
(gdb) 
0x00000d16	131		if (config->high_when_disabled) {
(gdb) 
136		if (config->output_enable) {
(gdb) 
0x00000d20	136		if (config->output_enable) {
(gdb) 
0x00000d22	136		if (config->output_enable) {
(gdb) 
141		if (config->division_factor > 1) {
(gdb) 
0x00000d2c	141		if (config->division_factor > 1) {
(gdb) 
0x00000d2e	141		if (config->division_factor > 1) {
(gdb) 
172		if (config->run_in_standby) {
(gdb) 
0x00000d62	172		if (config->run_in_standby) {
(gdb) 
0x00000d64	172		if (config->run_in_standby) {
(gdb) 
system_gclk_is_syncing (generator=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:70
70		 if (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 <SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 <SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 <SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 <SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 <SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 << generator )){
(gdb) 
system_gclk_gen_set_config (generator=0 '00', config=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:176
176		while (system_gclk_is_syncing(generator)) {
(gdb) 
0x00000d7a	176		while (system_gclk_is_syncing(generator)) {
(gdb) 
system_interrupt_enter_critical_section ()
    at ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:169
169		cpu_irq_enter_critical();
(gdb) 
0x00000d7e	169		cpu_irq_enter_critical();
(gdb) 
cpu_irq_enter_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:59
59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
0x00000116	59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
0x00000118	59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
0x0000011a	59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
__get_PRIMASK () at ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h:471
471	  __ASM volatile ("MRS %0, primask" : "=r" (result) );
(gdb) 
cpu_irq_enter_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:60
60			if (cpu_irq_is_enabled()) {
(gdb) 
0x00000122	60			if (cpu_irq_is_enabled()) {
(gdb) 
__disable_irq () at ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h:331
331	  __ASM volatile ("cpsid i");
(gdb) 
__DMB () at ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h:357
357	  __ASM volatile ("dmb");
(gdb) 
cpu_irq_enter_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:61
61				cpu_irq_disable();
(gdb) 
0x0000012c	61				cpu_irq_disable();
(gdb) 
0x0000012e	61				cpu_irq_disable();
(gdb) 
62				cpu_irq_prev_interrupt_state = true;
(gdb) 
0x00000132	62				cpu_irq_prev_interrupt_state = true;
(gdb) 
0x00000134	62				cpu_irq_prev_interrupt_state = true;
(gdb) 
0x00000136	62				cpu_irq_prev_interrupt_state = true;
(gdb) 
70		cpu_irq_critical_section_counter++;
(gdb) 
0x00000140	70		cpu_irq_critical_section_counter++;
(gdb) 
0x00000142	70		cpu_irq_critical_section_counter++;
(gdb) 
0x00000144	70		cpu_irq_critical_section_counter++;
(gdb) 
71	}
(gdb) 
0x00000d80 in system_interrupt_enter_critical_section ()
    at ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:169
169		cpu_irq_enter_critical();
(gdb) 
0x00000d82	169		cpu_irq_enter_critical();
(gdb) 
0x00000d84	169		cpu_irq_enter_critical();
(gdb) 
system_gclk_gen_set_config (generator=, config=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:182
182		GCLK->GENCTRL[generator].reg = new_genctrl_config | (GCLK->GENCTRL[generator].reg & GCLK_GENCTRL_GENEN);
(gdb) 
0x00000d88	182		GCLK->GENCTRL[generator].reg = new_genctrl_config | (GCLK->GENCTRL[generator].reg & GCLK_GENCTRL_GENEN);
(gdb) 
0x00000d8a	182		GCLK->GENCTRL[generator].reg = new_genctrl_config | (GCLK->GENCTRL[generator].reg & GCLK_GENCTRL_GENEN);
(gdb) 
0x00000d8c	182		GCLK->GENCTRL[generator].reg = new_genctrl_config | (GCLK->GENCTRL[generator].reg & GCLK_GENCTRL_GENEN);
(gdb) 
0x00000d8e	182		GCLK->GENCTRL[generator].reg = new_genctrl_config | (GCLK->GENCTRL[generator].reg & GCLK_GENCTRL_GENEN);
(gdb) 
0x00000d90	182		GCLK->GENCTRL[generator].reg = new_genctrl_config | (GCLK->GENCTRL[generator].reg & GCLK_GENCTRL_GENEN);
(gdb) 
system_gclk_is_syncing (generator=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:70
70		 if (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 <SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 <SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 <SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 << generator )){
(gdb) 
system_gclk_gen_set_config (generator=, config=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:184
184		while (system_gclk_is_syncing(generator)) {
(gdb) 
0x00000d9c	184		while (system_gclk_is_syncing(generator)) {
(gdb) 
system_interrupt_leave_critical_section ()
    at ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:182
182		cpu_irq_leave_critical();
(gdb) 
0x00000da0	182		cpu_irq_leave_critical();
(gdb) 
cpu_irq_leave_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:78
78		cpu_irq_critical_section_counter--;
(gdb) 
0x00000156	78		cpu_irq_critical_section_counter--;
(gdb) 
0x00000158	78		cpu_irq_critical_section_counter--;
(gdb) 
0x0000015a	78		cpu_irq_critical_section_counter--;
(gdb) 
82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x0000015e	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000160	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000162	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000164	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000166	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000168	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
83			cpu_irq_enable();
(gdb) 
0x0000016c	83			cpu_irq_enable();
(gdb) 
0x0000016e	83			cpu_irq_enable();
(gdb) 
__DMB () at ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h:357
357	  __ASM volatile ("dmb");
(gdb) 
__enable_irq () at ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h:320
320	  __ASM volatile ("cpsie i");
(gdb) 
cpu_irq_leave_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:85
85	}
(gdb) 
system_gclk_gen_set_config (generator=, config=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:189
189	}
(gdb) 
0x00000c2c in system_clock_init () at ../src/ASF/sam0/drivers/system/clock/clock_saml21/clock.c:1008
1008		_CONF_CLOCK_GCLK_CONFIG(0, ~);
(gdb) 
0x00000c2e	1008		_CONF_CLOCK_GCLK_CONFIG(0, ~);
(gdb) 
0x00000c30	1008		_CONF_CLOCK_GCLK_CONFIG(0, ~);
(gdb) 
system_gclk_gen_enable (generator=0 '00') at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:201
201	{
(gdb) 
0x00000db6	201	{
(gdb) 
system_gclk_is_syncing (generator=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:70
70		 if (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 <SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 <SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 <SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 <SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 <SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 << generator )){
(gdb) 
system_gclk_gen_enable (generator=0 '00') at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:202
202		while (system_gclk_is_syncing(generator)) {
(gdb) 
0x00000dc6	202		while (system_gclk_is_syncing(generator)) {
(gdb) 
system_interrupt_enter_critical_section ()
    at ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:169
169		cpu_irq_enter_critical();
(gdb) 
0x00000dca	169		cpu_irq_enter_critical();
(gdb) 
cpu_irq_enter_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:59
59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
0x00000116	59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
0x00000118	59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
0x0000011a	59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
__get_PRIMASK () at ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h:471
471	  __ASM volatile ("MRS %0, primask" : "=r" (result) );
(gdb) 
cpu_irq_enter_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:60
60			if (cpu_irq_is_enabled()) {
(gdb) 
0x00000122	60			if (cpu_irq_is_enabled()) {
(gdb) 
__disable_irq () at ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h:331
331	  __ASM volatile ("cpsid i");
(gdb) 
__DMB () at ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h:357
357	  __ASM volatile ("dmb");
(gdb) 
cpu_irq_enter_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:61
61				cpu_irq_disable();
(gdb) 
0x0000012c	61				cpu_irq_disable();
(gdb) 
0x0000012e	61				cpu_irq_disable();
(gdb) 
62				cpu_irq_prev_interrupt_state = true;
(gdb) 
0x00000132	62				cpu_irq_prev_interrupt_state = true;
(gdb) 
0x00000134	62				cpu_irq_prev_interrupt_state = true;
(gdb) 
0x00000136	62				cpu_irq_prev_interrupt_state = true;
(gdb) 
70		cpu_irq_critical_section_counter++;
(gdb) 
0x00000140	70		cpu_irq_critical_section_counter++;
(gdb) 
0x00000142	70		cpu_irq_critical_section_counter++;
(gdb) 
0x00000144	70		cpu_irq_critical_section_counter++;
(gdb) 
71	}
(gdb) 
0x00000dcc in system_interrupt_enter_critical_section ()
    at ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:169
169		cpu_irq_enter_critical();
(gdb) 
0x00000dce	169		cpu_irq_enter_critical();
(gdb) 
0x00000dd0	169		cpu_irq_enter_critical();
(gdb) 
system_gclk_gen_enable (generator=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:209
209		GCLK->GENCTRL[generator].reg |= GCLK_GENCTRL_GENEN;
(gdb) 
0x00000dd4	209		GCLK->GENCTRL[generator].reg |= GCLK_GENCTRL_GENEN;
(gdb) 
0x00000dd6	209		GCLK->GENCTRL[generator].reg |= GCLK_GENCTRL_GENEN;
(gdb) 
0x00000dd8	209		GCLK->GENCTRL[generator].reg |= GCLK_GENCTRL_GENEN;
(gdb) 
0x00000dda	209		GCLK->GENCTRL[generator].reg |= GCLK_GENCTRL_GENEN;
(gdb) 
system_interrupt_leave_critical_section ()
    at ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:182
182		cpu_irq_leave_critical();
(gdb) 
0x00000dde	182		cpu_irq_leave_critical();
(gdb) 
cpu_irq_leave_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:78
78		cpu_irq_critical_section_counter--;
(gdb) 
0x00000156	78		cpu_irq_critical_section_counter--;
(gdb) 
0x00000158	78		cpu_irq_critical_section_counter--;
(gdb) 
0x0000015a	78		cpu_irq_critical_section_counter--;
(gdb) 
82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x0000015e	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000160	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000162	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000164	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000166	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000168	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
83			cpu_irq_enable();
(gdb) 
0x0000016c	83			cpu_irq_enable();
(gdb) 
0x0000016e	83			cpu_irq_enable();
(gdb) 
__DMB () at ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h:357
357	  __ASM volatile ("dmb");
(gdb) 
__enable_irq () at ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h:320
320	  __ASM volatile ("cpsie i");
(gdb) 
cpu_irq_leave_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:85
85	}
(gdb) 
system_gclk_gen_enable (generator=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:212
212	}
(gdb) 
system_cpu_clock_get_hz () at ../src/ASF/sam0/drivers/system/clock/clock_saml21/clock_feature.h:1021
1021		return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> (MCLK->CPUDIV.reg - 1));
(gdb) 
0x00000c34	1021		return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> (MCLK->CPUDIV.reg - 1));
(gdb) 
0x00000c36	1021		return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> (MCLK->CPUDIV.reg - 1));
(gdb) 
system_gclk_gen_get_hz (generator=0 '00') at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:276
276	{
(gdb) 
0x00000df6	276	{
(gdb) 
system_gclk_is_syncing (generator=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:70
70		 if (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 <SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 <SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 <SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 <SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 <SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 << generator )){
(gdb) 
system_gclk_gen_get_hz (generator=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:277
277		while (system_gclk_is_syncing(generator)) {
(gdb) 
0x00000e06	277		while (system_gclk_is_syncing(generator)) {
(gdb) 
system_interrupt_enter_critical_section ()
    at ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:169
169		cpu_irq_enter_critical();
(gdb) 
0x00000e0a	169		cpu_irq_enter_critical();
(gdb) 
cpu_irq_enter_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:59
59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
0x00000116	59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
0x00000118	59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
0x0000011a	59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
__get_PRIMASK () at ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h:471
471	  __ASM volatile ("MRS %0, primask" : "=r" (result) );
(gdb) 
cpu_irq_enter_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:60
60			if (cpu_irq_is_enabled()) {
(gdb) 
0x00000122	60			if (cpu_irq_is_enabled()) {
(gdb) 
__disable_irq () at ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h:331
331	  __ASM volatile ("cpsid i");
(gdb) 
__DMB () at ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h:357
357	  __ASM volatile ("dmb");
(gdb) 
cpu_irq_enter_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:61
61				cpu_irq_disable();
(gdb) 
0x0000012c	61				cpu_irq_disable();
(gdb) 
0x0000012e	61				cpu_irq_disable();
(gdb) 
62				cpu_irq_prev_interrupt_state = true;
(gdb) 
0x00000132	62				cpu_irq_prev_interrupt_state = true;
(gdb) 
0x00000134	62				cpu_irq_prev_interrupt_state = true;
(gdb) 
0x00000136	62				cpu_irq_prev_interrupt_state = true;
(gdb) 
70		cpu_irq_critical_section_counter++;
(gdb) 
0x00000140	70		cpu_irq_critical_section_counter++;
(gdb) 
0x00000142	70		cpu_irq_critical_section_counter++;
(gdb) 
0x00000144	70		cpu_irq_critical_section_counter++;
(gdb) 
71	}
(gdb) 
system_gclk_gen_get_hz (generator=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:285
285				(enum system_clock_source)GCLK->GENCTRL[generator].bit.SRC);
(gdb) 
0x00000e0e	285				(enum system_clock_source)GCLK->GENCTRL[generator].bit.SRC);
(gdb) 
0x00000e10	285				(enum system_clock_source)GCLK->GENCTRL[generator].bit.SRC);
(gdb) 
0x00000e12	285				(enum system_clock_source)GCLK->GENCTRL[generator].bit.SRC);
(gdb) 
0x00000e14	285				(enum system_clock_source)GCLK->GENCTRL[generator].bit.SRC);
(gdb) 
0x00000e16	285				(enum system_clock_source)GCLK->GENCTRL[generator].bit.SRC);
(gdb) 
284		uint32_t gen_input_hz = system_clock_source_get_hz(
(gdb) 
0x00000e1a	284		uint32_t gen_input_hz = system_clock_source_get_hz(
(gdb) 
system_clock_source_get_hz (clock_source=SYSTEM_CLOCK_SOURCE_OSC16M)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/clock.c:198
198	{
(gdb) 
199		switch (clock_source) {
(gdb) 
0x00000b14	199		switch (clock_source) {
(gdb) 
0x00000b16	199		switch (clock_source) {
(gdb) 
0x00000b18	199		switch (clock_source) {
(gdb) 
0x00000b1a	199		switch (clock_source) {
(gdb) 
0x00000b1c	199		switch (clock_source) {
(gdb) 
204			return (OSCCTRL->OSC16MCTRL.bit.FSEL+1)*4000000UL;
(gdb) 
0x00000b2c	204			return (OSCCTRL->OSC16MCTRL.bit.FSEL+1)*4000000UL;
(gdb) 
0x00000b2e	204			return (OSCCTRL->OSC16MCTRL.bit.FSEL+1)*4000000UL;
(gdb) 
0x00000b30	204			return (OSCCTRL->OSC16MCTRL.bit.FSEL+1)*4000000UL;
(gdb) 
0x00000b32	204			return (OSCCTRL->OSC16MCTRL.bit.FSEL+1)*4000000UL;
(gdb) 
0x00000b34	204			return (OSCCTRL->OSC16MCTRL.bit.FSEL+1)*4000000UL;
(gdb) 
0x00000b36	204			return (OSCCTRL->OSC16MCTRL.bit.FSEL+1)*4000000UL;
(gdb) 
0x00000b38	204			return (OSCCTRL->OSC16MCTRL.bit.FSEL+1)*4000000UL;
(gdb) 
242	}
(gdb) 
0x00000e1c in system_gclk_gen_get_hz (generator=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:284
284		uint32_t gen_input_hz = system_clock_source_get_hz(
(gdb) 
287		uint8_t divsel = GCLK->GENCTRL[generator].bit.DIVSEL;
(gdb) 
0x00000e20	287		uint8_t divsel = GCLK->GENCTRL[generator].bit.DIVSEL;
(gdb) 
0x00000e22	287		uint8_t divsel = GCLK->GENCTRL[generator].bit.DIVSEL;
(gdb) 
288		uint32_t divider = GCLK->GENCTRL[generator].bit.DIV;
(gdb) 
0x00000e26	288		uint32_t divider = GCLK->GENCTRL[generator].bit.DIV;
(gdb) 
system_interrupt_leave_critical_section ()
    at ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:182
182		cpu_irq_leave_critical();
(gdb) 
0x00000e2a	182		cpu_irq_leave_critical();
(gdb) 
cpu_irq_leave_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:78
78		cpu_irq_critical_section_counter--;
(gdb) 
0x00000156	78		cpu_irq_critical_section_counter--;
(gdb) 
0x00000158	78		cpu_irq_critical_section_counter--;
(gdb) 
0x0000015a	78		cpu_irq_critical_section_counter--;
(gdb) 
82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x0000015e	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000160	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000162	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000164	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000166	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000168	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
83			cpu_irq_enable();
(gdb) 
0x0000016c	83			cpu_irq_enable();
(gdb) 
0x0000016e	83			cpu_irq_enable();
(gdb) 
__DMB () at ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h:357
357	  __ASM volatile ("dmb");
(gdb) 
__enable_irq () at ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h:320
320	  __ASM volatile ("cpsie i");
(gdb) 
cpu_irq_leave_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:85
85	}
(gdb) 
system_gclk_gen_get_hz (generator=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:293
293		if (!divsel && divider > 1) {
(gdb) 
0x00000e2e	293		if (!divsel && divider > 1) {
(gdb) 
0x00000e30	293		if (!divsel && divider > 1) {
(gdb) 
0x00000e32	293		if (!divsel && divider > 1) {
(gdb) 
300	}
(gdb) 
0x00000e46	300	}
(gdb) 
0x00000c38 in system_cpu_clock_get_hz ()
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/clock_feature.h:1021
1021		return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> (MCLK->CPUDIV.reg - 1));
(gdb) 
0x00000c3a	1021		return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> (MCLK->CPUDIV.reg - 1));
(gdb) 
0x00000c3c	1021		return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> (MCLK->CPUDIV.reg - 1));
(gdb) 
system_clock_init () at ../src/ASF/sam0/drivers/system/clock/clock_saml21/clock.c:1013
1013		if (cpu_freq < SYSTEM_PERFORMANCE_LEVEL_0_MAX_FREQ) {
(gdb) 
0x00000c40	1013		if (cpu_freq < SYSTEM_PERFORMANCE_LEVEL_0_MAX_FREQ) {
(gdb) 
0x00000c42	1013		if (cpu_freq PLCFG.reg) {
(gdb) 
0x00000c46	741		if (performance_level == (enum system_performance_level)PM->PLCFG.reg) {
(gdb) 
0x00000c48	741		if (performance_level == (enum system_performance_level)PM->PLCFG.reg) {
(gdb) 
0x00000c4a	741		if (performance_level == (enum system_performance_level)PM->PLCFG.reg) {
(gdb) 
0x00000c4c	741		if (performance_level == (enum system_performance_level)PM->PLCFG.reg) {
(gdb) 
system_cpu_clock_get_hz () at ../src/ASF/sam0/drivers/system/clock/clock_saml21/clock_feature.h:1021
1021		return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> (MCLK->CPUDIV.reg - 1));
(gdb) 
0x00000c50	1021		return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> (MCLK->CPUDIV.reg - 1));
(gdb) 
0x00000c52	1021		return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> (MCLK->CPUDIV.reg - 1));
(gdb) 
system_gclk_gen_get_hz (generator=0 '00') at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:276
276	{
(gdb) 
0x00000df6	276	{
(gdb) 
system_gclk_is_syncing (generator=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:70
70		 if (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 <SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 <SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 <SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 <SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 <SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 << generator )){
(gdb) 
system_gclk_gen_get_hz (generator=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:277
277		while (system_gclk_is_syncing(generator)) {
(gdb) 
0x00000e06	277		while (system_gclk_is_syncing(generator)) {
(gdb) 
system_interrupt_enter_critical_section ()
    at ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:169
169		cpu_irq_enter_critical();
(gdb) 
0x00000e0a	169		cpu_irq_enter_critical();
(gdb) 
cpu_irq_enter_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:59
59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
0x00000116	59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
0x00000118	59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
0x0000011a	59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
__get_PRIMASK () at ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h:471
471	  __ASM volatile ("MRS %0, primask" : "=r" (result) );
(gdb) 
cpu_irq_enter_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:60
60			if (cpu_irq_is_enabled()) {
(gdb) 
0x00000122	60			if (cpu_irq_is_enabled()) {
(gdb) 
__disable_irq () at ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h:331
331	  __ASM volatile ("cpsid i");
(gdb) 
__DMB () at ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h:357
357	  __ASM volatile ("dmb");
(gdb) 
cpu_irq_enter_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:61
61				cpu_irq_disable();
(gdb) 
0x0000012c	61				cpu_irq_disable();
(gdb) 
0x0000012e	61				cpu_irq_disable();
(gdb) 
62				cpu_irq_prev_interrupt_state = true;
(gdb) 
0x00000132	62				cpu_irq_prev_interrupt_state = true;
(gdb) 
0x00000134	62				cpu_irq_prev_interrupt_state = true;
(gdb) 
0x00000136	62				cpu_irq_prev_interrupt_state = true;
(gdb) 
70		cpu_irq_critical_section_counter++;
(gdb) 
0x00000140	70		cpu_irq_critical_section_counter++;
(gdb) 
0x00000142	70		cpu_irq_critical_section_counter++;
(gdb) 
0x00000144	70		cpu_irq_critical_section_counter++;
(gdb) 
71	}
(gdb) 
system_gclk_gen_get_hz (generator=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:285
285				(enum system_clock_source)GCLK->GENCTRL[generator].bit.SRC);
(gdb) 
0x00000e0e	285				(enum system_clock_source)GCLK->GENCTRL[generator].bit.SRC);
(gdb) 
0x00000e10	285				(enum system_clock_source)GCLK->GENCTRL[generator].bit.SRC);
(gdb) 
0x00000e12	285				(enum system_clock_source)GCLK->GENCTRL[generator].bit.SRC);
(gdb) 
0x00000e14	285				(enum system_clock_source)GCLK->GENCTRL[generator].bit.SRC);
(gdb) 
0x00000e16	285				(enum system_clock_source)GCLK->GENCTRL[generator].bit.SRC);
(gdb) 
284		uint32_t gen_input_hz = system_clock_source_get_hz(
(gdb) 
0x00000e1a	284		uint32_t gen_input_hz = system_clock_source_get_hz(
(gdb) 
system_clock_source_get_hz (clock_source=SYSTEM_CLOCK_SOURCE_OSC16M)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/clock.c:198
198	{
(gdb) 
199		switch (clock_source) {
(gdb) 
0x00000b14	199		switch (clock_source) {
(gdb) 
0x00000b16	199		switch (clock_source) {
(gdb) 
0x00000b18	199		switch (clock_source) {
(gdb) 
0x00000b1a	199		switch (clock_source) {
(gdb) 
0x00000b1c	199		switch (clock_source) {
(gdb) 
204			return (OSCCTRL->OSC16MCTRL.bit.FSEL+1)*4000000UL;
(gdb) 
0x00000b2c	204			return (OSCCTRL->OSC16MCTRL.bit.FSEL+1)*4000000UL;
(gdb) 
0x00000b2e	204			return (OSCCTRL->OSC16MCTRL.bit.FSEL+1)*4000000UL;
(gdb) 
0x00000b30	204			return (OSCCTRL->OSC16MCTRL.bit.FSEL+1)*4000000UL;
(gdb) 
0x00000b32	204			return (OSCCTRL->OSC16MCTRL.bit.FSEL+1)*4000000UL;
(gdb) 
0x00000b34	204			return (OSCCTRL->OSC16MCTRL.bit.FSEL+1)*4000000UL;
(gdb) 
0x00000b36	204			return (OSCCTRL->OSC16MCTRL.bit.FSEL+1)*4000000UL;
(gdb) 
0x00000b38	204			return (OSCCTRL->OSC16MCTRL.bit.FSEL+1)*4000000UL;
(gdb) 
242	}
(gdb) 
0x00000e1c in system_gclk_gen_get_hz (generator=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:284
284		uint32_t gen_input_hz = system_clock_source_get_hz(
(gdb) 
287		uint8_t divsel = GCLK->GENCTRL[generator].bit.DIVSEL;
(gdb) 
0x00000e20	287		uint8_t divsel = GCLK->GENCTRL[generator].bit.DIVSEL;
(gdb) 
0x00000e22	287		uint8_t divsel = GCLK->GENCTRL[generator].bit.DIVSEL;
(gdb) 
288		uint32_t divider = GCLK->GENCTRL[generator].bit.DIV;
(gdb) 
0x00000e26	288		uint32_t divider = GCLK->GENCTRL[generator].bit.DIV;
(gdb) 
system_interrupt_leave_critical_section ()
    at ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:182
182		cpu_irq_leave_critical();
(gdb) 
0x00000e2a	182		cpu_irq_leave_critical();
(gdb) 
cpu_irq_leave_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:78
78		cpu_irq_critical_section_counter--;
(gdb) 
0x00000156	78		cpu_irq_critical_section_counter--;
(gdb) 
0x00000158	78		cpu_irq_critical_section_counter--;
(gdb) 
0x0000015a	78		cpu_irq_critical_section_counter--;
(gdb) 
82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x0000015e	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000160	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000162	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000164	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000166	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000168	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
83			cpu_irq_enable();
(gdb) 
0x0000016c	83			cpu_irq_enable();
(gdb) 
0x0000016e	83			cpu_irq_enable();
(gdb) 
__DMB () at ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h:357
357	  __ASM volatile ("dmb");
(gdb) 
__enable_irq () at ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h:320
320	  __ASM volatile ("cpsie i");
(gdb) 
cpu_irq_leave_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:85
85	}
(gdb) 
system_gclk_gen_get_hz (generator=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:293
293		if (!divsel && divider > 1) {
(gdb) 
0x00000e2e	293		if (!divsel && divider > 1) {
(gdb) 
0x00000e30	293		if (!divsel && divider > 1) {
(gdb) 
0x00000e32	293		if (!divsel && divider > 1) {
(gdb) 
300	}
(gdb) 
0x00000e46	300	}
(gdb) 
0x00000c54 in system_cpu_clock_get_hz ()
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/clock_feature.h:1021
1021		return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> (MCLK->CPUDIV.reg - 1));
(gdb) 
0x00000c56	1021		return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> (MCLK->CPUDIV.reg - 1));
(gdb) 
0x00000c58	1021		return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> (MCLK->CPUDIV.reg - 1));
(gdb) 
system_switch_performance_level (performance_level=SYSTEM_PERFORMANCE_LEVEL_0)
    at ../src/ASF/sam0/drivers/system/power/power_sam_l/power.h:745
745		if (system_cpu_clock_get_hz() >
(gdb) 
0x00000c5c	745		if (system_cpu_clock_get_hz() >
(gdb) 
0x00000c5e	745		if (system_cpu_clock_get_hz() >
(gdb) 
751		PM->INTFLAG.reg = PM_INTFLAG_PLRDY;
(gdb) 
0x00000c62	751		PM->INTFLAG.reg = PM_INTFLAG_PLRDY;
(gdb) 
0x00000c64	751		PM->INTFLAG.reg = PM_INTFLAG_PLRDY;
(gdb) 
0x00000c66	751		PM->INTFLAG.reg = PM_INTFLAG_PLRDY;
(gdb) 
754		PM->PLCFG.reg = performance_level;
(gdb) 
0x00000c6a	754		PM->PLCFG.reg = performance_level;
(gdb) 
757		while (!PM->INTFLAG.reg) {
(gdb) 
0x00000c6e	757		while (!PM->INTFLAG.reg) {
(gdb) 
0x00000c70	757		while (!PM->INTFLAG.reg) {
(gdb) 
0x00000c72	757		while (!PM->INTFLAG.reg) {
(gdb) 
0x00000c74	757		while (!PM->INTFLAG.reg) {
(gdb) 
system_clock_init () at ../src/ASF/sam0/drivers/system/clock/clock_saml21/clock.c:1018
1018	}
(gdb) 
0x00000cae in system_clock_init () at ../src/ASF/sam0/drivers/system/clock/clock_saml21/clock.c:1018
1018	}
(gdb) 
system_init () at ../src/ASF/sam0/drivers/system/system.c:97
97		system_board_init();
(gdb) 
0x00000fe0	97		system_board_init();
(gdb) 
system_board_init () at ../src/ASF/sam0/boards/saml21_xplained_pro/board_init.c:60
60	{
(gdb) 
0x00000186	60	{
(gdb) 
port_get_config_defaults (config=0x20002084) at ../src/ASF/sam0/drivers/port/port.h:435
435		config->input_pull = PORT_PIN_PULL_UP;
(gdb) 
0x0000018a	435		config->input_pull = PORT_PIN_PULL_UP;
(gdb) 
0x0000018c	435		config->input_pull = PORT_PIN_PULL_UP;
(gdb) 
436		config->powersave  = false;
(gdb) 
0x00000190	436		config->powersave  = false;
(gdb) 
system_board_init () at ../src/ASF/sam0/boards/saml21_xplained_pro/board_init.c:65
65		pin_conf.direction  = PORT_PIN_DIR_OUTPUT;
(gdb) 
66		port_pin_set_config(LED_0_PIN, &pin_conf);
(gdb) 
0x00000196	66		port_pin_set_config(LED_0_PIN, &pin_conf);
(gdb) 
0x00000198	66		port_pin_set_config(LED_0_PIN, &pin_conf);
(gdb) 
0x0000019a	66		port_pin_set_config(LED_0_PIN, &pin_conf);
(gdb) 
port_pin_set_config (gpio_pin=42 '*', config=0x20002084) at ../src/ASF/sam0/drivers/port/port.c:63
63	{
(gdb) 
0x000001be	63	{
(gdb) 
system_pinmux_get_config_defaults (config=0x20002074) at ../src/ASF/sam0/drivers/system/pinmux/pinmux.h:311
311		config->mux_position = SYSTEM_PINMUX_GPIO;
(gdb) 
0x000001c2	311		config->mux_position = SYSTEM_PINMUX_GPIO;
(gdb) 
0x000001c4	311		config->mux_position = SYSTEM_PINMUX_GPIO;
(gdb) 
port_pin_set_config (gpio_pin=42 '*', config=0x20002084) at ../src/ASF/sam0/drivers/port/port.c:71
71		pinmux_config.direction    = (enum system_pinmux_pin_dir)config->direction;
(gdb) 
0x000001c8	71		pinmux_config.direction    = (enum system_pinmux_pin_dir)config->direction;
(gdb) 
72		pinmux_config.input_pull   = (enum system_pinmux_pin_pull)config->input_pull;
(gdb) 
0x000001cc	72		pinmux_config.input_pull   = (enum system_pinmux_pin_pull)config->input_pull;
(gdb) 
73		pinmux_config.powersave    = config->powersave;
(gdb) 
0x000001d0	73		pinmux_config.powersave    = config->powersave;
(gdb) 
75		system_pinmux_pin_set_config(gpio_pin, &pinmux_config);
(gdb) 
0x000001d4	75		system_pinmux_pin_set_config(gpio_pin, &pinmux_config);
(gdb) 
0x000001d6	75		system_pinmux_pin_set_config(gpio_pin, &pinmux_config);
(gdb) 
system_pinmux_pin_set_config (gpio_pin=42 '*', config=0x20002074)
    at ../src/ASF/sam0/drivers/system/pinmux/pinmux.c:163
163	{
(gdb) 
0x00000faa	163	{
(gdb) 
0x00000fac	163	{
(gdb) 
system_pinmux_get_group_from_gpio_pin (gpio_pin=42 '*')
    at ../src/ASF/sam0/drivers/system/pinmux/pinmux.h:351
351		if (port_index < PORT_INST_NUM) {
(gdb) 
355			return NULL;
(gdb) 
351		if (port_index < PORT_INST_NUM) {
(gdb) 
0x00000fb4	351		if (port_index Group[group_index]);
(gdb) 
0x00000fb8	352			return &(ports[port_index]->Group[group_index]);
(gdb) 
0x00000fba	352			return &(ports[port_index]->Group[group_index]);
(gdb) 
0x00000fbc	352			return &(ports[port_index]->Group[group_index]);
(gdb) 
system_pinmux_pin_set_config (gpio_pin=, config=0x20002074)
    at ../src/ASF/sam0/drivers/system/pinmux/pinmux.c:165
165		uint32_t pin_mask = (1UL << (gpio_pin % 32));
(gdb) 
0x00000fc0	165		uint32_t pin_mask = (1UL << (gpio_pin % 32));
(gdb) 
0x00000fc2	165		uint32_t pin_mask = (1UL << (gpio_pin % 32));
(gdb) 
0x00000fc4	165		uint32_t pin_mask = (1UL <powersave) {
(gdb) 
0x00000f20	72		if (!config->powersave) {
(gdb) 
0x00000f22	72		if (!config->powersave) {
(gdb) 
75			if (config->mux_position != SYSTEM_PINMUX_GPIO) {
(gdb) 
0x00000f26	75			if (config->mux_position != SYSTEM_PINMUX_GPIO) {
(gdb) 
0x00000f28	75			if (config->mux_position != SYSTEM_PINMUX_GPIO) {
(gdb) 
69		uint32_t pin_cfg = 0;
(gdb) 
81			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_INPUT) ||
(gdb) 
0x00000f38	81			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_INPUT) ||
(gdb) 
0x00000f3a	81			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_INPUT) ||
(gdb) 
0x00000f3c	81			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_INPUT) ||
(gdb) 
96			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
(gdb) 
0x00000f56	96			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
(gdb) 
0x00000f58	96			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
(gdb) 
0x00000f5a	96			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
(gdb) 
101				pin_cfg &= ~PORT_WRCONFIG_PULLEN;
(gdb) 
0x00000f5e	101				pin_cfg &= ~PORT_WRCONFIG_PULLEN;
(gdb) 
0x00000f60	101				pin_cfg &= ~PORT_WRCONFIG_PULLEN;
(gdb) 
109		uint32_t lower_pin_mask = (pin_mask & 0xFFFF);
(gdb) 
0x00000f68	109		uint32_t lower_pin_mask = (pin_mask & 0xFFFF);
(gdb) 
115			= (lower_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
(gdb) 
0x00000f6c	115			= (lower_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
(gdb) 
0x00000f6e	115			= (lower_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
(gdb) 
116				pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG;
(gdb) 
115			= (lower_pin_mask <> 16);
(gdb) 
121			= (upper_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
(gdb) 
0x00000f78	121			= (upper_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
(gdb) 
0x00000f7a	121			= (upper_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
(gdb) 
122				pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG |
(gdb) 
121			= (upper_pin_mask <powersave) {
(gdb) 
0x00000f82	125		if(!config->powersave) {
(gdb) 
0x00000f84	125		if(!config->powersave) {
(gdb) 
129			if (pin_cfg & PORT_WRCONFIG_PULLEN) {
(gdb) 
0x00000f88	129			if (pin_cfg & PORT_WRCONFIG_PULLEN) {
(gdb) 
140			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
(gdb) 
0x00000f98	140			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
(gdb) 
0x00000f9a	140			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
(gdb) 
0x00000f9c	140			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
(gdb) 
143				port->DIRSET.reg = pin_mask;
(gdb) 
146	}
(gdb) 
system_pinmux_pin_set_config (gpio_pin=, config=)
    at ../src/ASF/sam0/drivers/system/pinmux/pinmux.c:168
168	}
(gdb) 
port_pin_set_config (gpio_pin=, config=)
    at ../src/ASF/sam0/drivers/port/port.c:76
76	}
(gdb) 
0x000001da in port_pin_set_config (gpio_pin=, config=)
    at ../src/ASF/sam0/drivers/port/port.c:76
76	}
(gdb) 
port_pin_set_output_level (level=true, gpio_pin=42 '*') at ../src/ASF/sam0/drivers/port/port.h:509
509			port_base->OUTSET.reg = pin_mask;
(gdb) 
0x0000019e	509			port_base->OUTSET.reg = pin_mask;
(gdb) 
0x000001a0	509			port_base->OUTSET.reg = pin_mask;
(gdb) 
0x000001a2	509			port_base->OUTSET.reg = pin_mask;
(gdb) 
system_board_init () at ../src/ASF/sam0/boards/saml21_xplained_pro/board_init.c:70
70		pin_conf.direction  = PORT_PIN_DIR_INPUT;
(gdb) 
71		pin_conf.input_pull = PORT_PIN_PULL_UP;
(gdb) 
72		port_pin_set_config(BUTTON_0_PIN, &pin_conf);
(gdb) 
0x000001aa	72		port_pin_set_config(BUTTON_0_PIN, &pin_conf);
(gdb) 
0x000001ac	72		port_pin_set_config(BUTTON_0_PIN, &pin_conf);
(gdb) 
port_pin_set_config (gpio_pin=2 '02', config=0x20002084) at ../src/ASF/sam0/drivers/port/port.c:63
63	{
(gdb) 
0x000001be	63	{
(gdb) 
system_pinmux_get_config_defaults (config=0x20002074) at ../src/ASF/sam0/drivers/system/pinmux/pinmux.h:311
311		config->mux_position = SYSTEM_PINMUX_GPIO;
(gdb) 
0x000001c2	311		config->mux_position = SYSTEM_PINMUX_GPIO;
(gdb) 
0x000001c4	311		config->mux_position = SYSTEM_PINMUX_GPIO;
(gdb) 
port_pin_set_config (gpio_pin=2 '02', config=0x20002084) at ../src/ASF/sam0/drivers/port/port.c:71
71		pinmux_config.direction    = (enum system_pinmux_pin_dir)config->direction;
(gdb) 
0x000001c8	71		pinmux_config.direction    = (enum system_pinmux_pin_dir)config->direction;
(gdb) 
72		pinmux_config.input_pull   = (enum system_pinmux_pin_pull)config->input_pull;
(gdb) 
0x000001cc	72		pinmux_config.input_pull   = (enum system_pinmux_pin_pull)config->input_pull;
(gdb) 
73		pinmux_config.powersave    = config->powersave;
(gdb) 
0x000001d0	73		pinmux_config.powersave    = config->powersave;
(gdb) 
75		system_pinmux_pin_set_config(gpio_pin, &pinmux_config);
(gdb) 
0x000001d4	75		system_pinmux_pin_set_config(gpio_pin, &pinmux_config);
(gdb) 
0x000001d6	75		system_pinmux_pin_set_config(gpio_pin, &pinmux_config);
(gdb) 
system_pinmux_pin_set_config (gpio_pin=2 '02', config=0x20002074)
    at ../src/ASF/sam0/drivers/system/pinmux/pinmux.c:163
163	{
(gdb) 
0x00000faa	163	{
(gdb) 
0x00000fac	163	{
(gdb) 
system_pinmux_get_group_from_gpio_pin (gpio_pin=2 '02')
    at ../src/ASF/sam0/drivers/system/pinmux/pinmux.h:351
351		if (port_index < PORT_INST_NUM) {
(gdb) 
355			return NULL;
(gdb) 
351		if (port_index < PORT_INST_NUM) {
(gdb) 
0x00000fb4	351		if (port_index Group[group_index]);
(gdb) 
0x00000fb8	352			return &(ports[port_index]->Group[group_index]);
(gdb) 
0x00000fba	352			return &(ports[port_index]->Group[group_index]);
(gdb) 
0x00000fbc	352			return &(ports[port_index]->Group[group_index]);
(gdb) 
system_pinmux_pin_set_config (gpio_pin=, config=0x20002074)
    at ../src/ASF/sam0/drivers/system/pinmux/pinmux.c:165
165		uint32_t pin_mask = (1UL << (gpio_pin % 32));
(gdb) 
0x00000fc0	165		uint32_t pin_mask = (1UL << (gpio_pin % 32));
(gdb) 
0x00000fc2	165		uint32_t pin_mask = (1UL << (gpio_pin % 32));
(gdb) 
0x00000fc4	165		uint32_t pin_mask = (1UL <powersave) {
(gdb) 
0x00000f20	72		if (!config->powersave) {
(gdb) 
0x00000f22	72		if (!config->powersave) {
(gdb) 
75			if (config->mux_position != SYSTEM_PINMUX_GPIO) {
(gdb) 
0x00000f26	75			if (config->mux_position != SYSTEM_PINMUX_GPIO) {
(gdb) 
0x00000f28	75			if (config->mux_position != SYSTEM_PINMUX_GPIO) {
(gdb) 
69		uint32_t pin_cfg = 0;
(gdb) 
81			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_INPUT) ||
(gdb) 
0x00000f38	81			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_INPUT) ||
(gdb) 
0x00000f3a	81			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_INPUT) ||
(gdb) 
0x00000f3c	81			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_INPUT) ||
(gdb) 
87				if (config->input_pull != SYSTEM_PINMUX_PIN_PULL_NONE) {
(gdb) 
0x00000f40	87				if (config->input_pull != SYSTEM_PINMUX_PIN_PULL_NONE) {
(gdb) 
0x00000f42	87				if (config->input_pull != SYSTEM_PINMUX_PIN_PULL_NONE) {
(gdb) 
88					pin_cfg |= PORT_WRCONFIG_PULLEN;
(gdb) 
0x00000f4e	88					pin_cfg |= PORT_WRCONFIG_PULLEN;
(gdb) 
0x00000f50	88					pin_cfg |= PORT_WRCONFIG_PULLEN;
(gdb) 
92				port->DIRCLR.reg = pin_mask;
(gdb) 
96			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
(gdb) 
0x00000f56	96			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
(gdb) 
0x00000f58	96			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
(gdb) 
0x00000f5a	96			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
(gdb) 
109		uint32_t lower_pin_mask = (pin_mask & 0xFFFF);
(gdb) 
0x00000f68	109		uint32_t lower_pin_mask = (pin_mask & 0xFFFF);
(gdb) 
115			= (lower_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
(gdb) 
0x00000f6c	115			= (lower_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
(gdb) 
0x00000f6e	115			= (lower_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
(gdb) 
116				pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG;
(gdb) 
115			= (lower_pin_mask <> 16);
(gdb) 
121			= (upper_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
(gdb) 
0x00000f78	121			= (upper_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
(gdb) 
0x00000f7a	121			= (upper_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
(gdb) 
122				pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG |
(gdb) 
121			= (upper_pin_mask <powersave) {
(gdb) 
0x00000f82	125		if(!config->powersave) {
(gdb) 
0x00000f84	125		if(!config->powersave) {
(gdb) 
129			if (pin_cfg & PORT_WRCONFIG_PULLEN) {
(gdb) 
0x00000f88	129			if (pin_cfg & PORT_WRCONFIG_PULLEN) {
(gdb) 
132				if (config->input_pull == SYSTEM_PINMUX_PIN_PULL_UP) {
(gdb) 
0x00000f8c	132				if (config->input_pull == SYSTEM_PINMUX_PIN_PULL_UP) {
(gdb) 
0x00000f8e	132				if (config->input_pull == SYSTEM_PINMUX_PIN_PULL_UP) {
(gdb) 
133					port->OUTSET.reg = pin_mask;
(gdb) 
0x00000f92	133					port->OUTSET.reg = pin_mask;
(gdb) 
140			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
(gdb) 
0x00000f98	140			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
(gdb) 
0x00000f9a	140			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
(gdb) 
0x00000f9c	140			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
(gdb) 
146	}
(gdb) 
system_pinmux_pin_set_config (gpio_pin=, config=)
    at ../src/ASF/sam0/drivers/system/pinmux/pinmux.c:168
168	}
(gdb) 
port_pin_set_config (gpio_pin=, config=)
    at ../src/ASF/sam0/drivers/port/port.c:76
76	}
(gdb) 
0x000001da in port_pin_set_config (gpio_pin=, config=)
    at ../src/ASF/sam0/drivers/port/port.c:76
76	}
(gdb) 
system_board_init () at ../src/ASF/sam0/boards/saml21_xplained_pro/board_init.c:73
73	}
(gdb) 
0x000001b0 in system_board_init () at ../src/ASF/sam0/boards/saml21_xplained_pro/board_init.c:73
73	}
(gdb) 
system_init () at ../src/ASF/sam0/drivers/system/system.c:100
100		_system_events_init();
(gdb) 
0x00000fe4	100		_system_events_init();
(gdb) 
_system_dummy_init () at ../src/ASF/sam0/drivers/system/system.c:58
58	}
(gdb) 
system_init () at ../src/ASF/sam0/drivers/system/system.c:103
103		_system_extint_init();
(gdb) 
0x00000fe8	103		_system_extint_init();
(gdb) 
_system_dummy_init () at ../src/ASF/sam0/drivers/system/system.c:58
58	}
(gdb) 
system_init () at ../src/ASF/sam0/drivers/system/system.c:104
104	}
(gdb) 
main () at ../src/qs_i2c_master_callback.c:136
136		configure_i2c();
(gdb) 
0x00001180	136		configure_i2c();
(gdb) 
configure_i2c () at ../src/qs_i2c_master_callback.c:90
90	{
(gdb) 
0x000010aa	90	{
(gdb) 
i2c_master_get_config_defaults (config=0x20002068) at ../src/ASF/sam0/drivers/sercom/i2c/i2c_master.h:438
438		config->baud_rate        = I2C_MASTER_BAUD_RATE_100KHZ;
(gdb) 
0x000010ae	438		config->baud_rate        = I2C_MASTER_BAUD_RATE_100KHZ;
(gdb) 
440		config->baud_rate_high_speed = I2C_MASTER_BAUD_RATE_3400KHZ;
(gdb) 
0x000010b2	440		config->baud_rate_high_speed = I2C_MASTER_BAUD_RATE_3400KHZ;
(gdb) 
441		config->transfer_speed       = I2C_MASTER_SPEED_STANDARD_AND_FAST;
(gdb) 
0x000010b6	441		config->transfer_speed       = I2C_MASTER_SPEED_STANDARD_AND_FAST;
(gdb) 
443		config->generator_source = GCLK_GENERATOR_0;
(gdb) 
0x000010ba	443		config->generator_source = GCLK_GENERATOR_0;
(gdb) 
444		config->run_in_standby   = false;
(gdb) 
445		config->start_hold_time  = I2C_MASTER_START_HOLD_TIME_300NS_600NS;
(gdb) 
0x000010c0	445		config->start_hold_time  = I2C_MASTER_START_HOLD_TIME_300NS_600NS;
(gdb) 
0x000010c2	445		config->start_hold_time  = I2C_MASTER_START_HOLD_TIME_300NS_600NS;
(gdb) 
446		config->buffer_timeout   = 65535;
(gdb) 
0x000010c6	446		config->buffer_timeout   = 65535;
(gdb) 
0x000010c8	446		config->buffer_timeout   = 65535;
(gdb) 
447		config->unknown_bus_state_timeout = 65535;
(gdb) 
448		config->pinmux_pad0      = PINMUX_DEFAULT;
(gdb) 
449		config->pinmux_pad1      = PINMUX_DEFAULT;
(gdb) 
450		config->scl_low_timeout  = false;
(gdb) 
0x000010d2	450		config->scl_low_timeout  = false;
(gdb) 
451		config->inactive_timeout = I2C_MASTER_INACTIVE_TIMEOUT_DISABLED;
(gdb) 
453		config->scl_stretch_only_after_ack_bit = false;
(gdb) 
0x000010d8	453		config->scl_stretch_only_after_ack_bit = false;
(gdb) 
456		config->slave_scl_low_extend_timeout   = false;
(gdb) 
0x000010dc	456		config->slave_scl_low_extend_timeout   = false;
(gdb) 
457		config->master_scl_low_extend_timeout  = false;
(gdb) 
0x000010e0	457		config->master_scl_low_extend_timeout  = false;
(gdb) 
configure_i2c () at ../src/qs_i2c_master_callback.c:104
104		while(i2c_master_init(&i2c_master_instance, SERCOM2, &config_i2c_master)     \
(gdb) 
0x000010e4	104		while(i2c_master_init(&i2c_master_instance, SERCOM2, &config_i2c_master)     \
(gdb) 
0x000010e6	104		while(i2c_master_init(&i2c_master_instance, SERCOM2, &config_i2c_master)     \
(gdb) 
0x000010e8	104		while(i2c_master_init(&i2c_master_instance, SERCOM2, &config_i2c_master)     \
(gdb) 
0x000010ea	104		while(i2c_master_init(&i2c_master_instance, SERCOM2, &config_i2c_master)     \
(gdb) 
0x000010ec	104		while(i2c_master_init(&i2c_master_instance, SERCOM2, &config_i2c_master)     \
(gdb) 
0x000010ee	104		while(i2c_master_init(&i2c_master_instance, SERCOM2, &config_i2c_master)     \
(gdb) 
i2c_master_init (module=0x2000008c , hw=0x42000800, config=0x20002068)
    at ../src/ASF/sam0/drivers/sercom/i2c/i2c_samd21_r21_d10_d11_l21/i2c_master.c:230
230	{
(gdb) 
0x000001e2	230	{
(gdb) 
0x000001e4	230	{
(gdb) 
0x000001e6	230	{
(gdb) 
0x000001e8	230	{
(gdb) 
0x000001ea	230	{
(gdb) 
0x000001ec	230	{
(gdb) 
237		module->hw = hw;
(gdb) 
241		uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
(gdb) 
0x000001f2	241		uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
(gdb) 
0x000001f4	241		uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
(gdb) 
_sercom_get_sercom_inst_index (sercom_instance=0x42000800) at ../src/ASF/sam0/drivers/sercom/sercom.c:282
282	{
(gdb) 
0x00000a0a	282	{
(gdb) 
284		Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
(gdb) 
0x00000a0e	284		Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
(gdb) 
0x00000a10	284		Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
(gdb) 
0x00000a12	284		Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
(gdb) 
0x00000a14	284		Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
(gdb) 
0x00000a16	284		Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
(gdb) 
288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
0x00000a1a	288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
0x00000a1c	288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
287		for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
(gdb) 
0x00000a20	287		for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
(gdb) 
288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
0x00000a24	288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
0x00000a26	288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
0x00000a28	288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
287		for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
(gdb) 
0x00000a34	287		for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
(gdb) 
0x00000a36	287		for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
(gdb) 
0x00000a20	287		for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
(gdb) 
288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
0x00000a24	288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
0x00000a26	288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
0x00000a28	288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
0x00000a2a	288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
289				return i;
(gdb) 
0x00000a30	289				return i;
(gdb) 
296	}
(gdb) 
0x00000a3c in _sercom_get_sercom_inst_index (sercom_instance=)
    at ../src/ASF/sam0/drivers/sercom/sercom.c:296
296	}
(gdb) 
system_apb_clock_set_mask (mask=4, bus=SYSTEM_CLOCK_APB_APBC)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/clock_feature.h:1124
1124				MCLK->APBCMASK.reg |= mask;
(gdb) 
0x000001f8	1124				MCLK->APBCMASK.reg |= mask;
(gdb) 
i2c_master_init (module=0x2000008c , hw=0x42000800, config=0x20002068)
    at ../src/ASF/sam0/drivers/sercom/i2c/i2c_samd21_r21_d10_d11_l21/i2c_master.c:250
250		system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
(gdb) 
0x000001fc	250		system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 <APBCMASK.reg |= mask;
(gdb) 
0x00000200	1124				MCLK->APBCMASK.reg |= mask;
(gdb) 
i2c_master_init (module=0x2000008c , hw=0x42000800, config=0x20002068)
    at ../src/ASF/sam0/drivers/sercom/i2c/i2c_samd21_r21_d10_d11_l21/i2c_master.c:255
255		gclk_chan_conf.source_generator = config->generator_source;
(gdb) 
0x00000204	255		gclk_chan_conf.source_generator = config->generator_source;
(gdb) 
0x00000206	255		gclk_chan_conf.source_generator = config->generator_source;
(gdb) 
247		uint32_t gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
(gdb) 
0x0000020a	247		uint32_t gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
(gdb) 
256		system_gclk_chan_set_config(gclk_index, &gclk_chan_conf);
(gdb) 
0x0000020e	256		system_gclk_chan_set_config(gclk_index, &gclk_chan_conf);
(gdb) 
0x00000210	256		system_gclk_chan_set_config(gclk_index, &gclk_chan_conf);
(gdb) 
0x00000212	256		system_gclk_chan_set_config(gclk_index, &gclk_chan_conf);
(gdb) 
system_gclk_chan_set_config (channel=20 '24', config=0x2000204c)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:318
318	{
(gdb) 
0x00000eca	318	{
(gdb) 
0x00000ecc	318	{
(gdb) 
323		system_gclk_chan_disable(channel);
(gdb) 
0x00000ed0	323		system_gclk_chan_disable(channel);
(gdb) 
system_gclk_chan_disable (channel=20 '24')
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:364
364	{
(gdb) 
0x00000e96	364	{
(gdb) 
system_interrupt_enter_critical_section ()
    at ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:169
169		cpu_irq_enter_critical();
(gdb) 
0x00000e9a	169		cpu_irq_enter_critical();
(gdb) 
cpu_irq_enter_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:59
59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
0x00000116	59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
0x00000118	59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
0x0000011a	59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
__get_PRIMASK () at ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h:471
471	  __ASM volatile ("MRS %0, primask" : "=r" (result) );
(gdb) 
cpu_irq_enter_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:60
60			if (cpu_irq_is_enabled()) {
(gdb) 
0x00000122	60			if (cpu_irq_is_enabled()) {
(gdb) 
__disable_irq () at ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h:331
331	  __ASM volatile ("cpsid i");
(gdb) 
__DMB () at ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h:357
357	  __ASM volatile ("dmb");
(gdb) 
cpu_irq_enter_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:61
61				cpu_irq_disable();
(gdb) 
0x0000012c	61				cpu_irq_disable();
(gdb) 
0x0000012e	61				cpu_irq_disable();
(gdb) 
62				cpu_irq_prev_interrupt_state = true;
(gdb) 
0x00000132	62				cpu_irq_prev_interrupt_state = true;
(gdb) 
0x00000134	62				cpu_irq_prev_interrupt_state = true;
(gdb) 
0x00000136	62				cpu_irq_prev_interrupt_state = true;
(gdb) 
70		cpu_irq_critical_section_counter++;
(gdb) 
0x00000140	70		cpu_irq_critical_section_counter++;
(gdb) 
0x00000142	70		cpu_irq_critical_section_counter++;
(gdb) 
0x00000144	70		cpu_irq_critical_section_counter++;
(gdb) 
71	}
(gdb) 
0x00000e9c in system_interrupt_enter_critical_section ()
    at ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:169
169		cpu_irq_enter_critical();
(gdb) 
0x00000e9e	169		cpu_irq_enter_critical();
(gdb) 
0x00000ea0	169		cpu_irq_enter_critical();
(gdb) 
system_gclk_chan_disable (channel=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:371
371		GCLK->PCHCTRL[channel].reg &= ~GCLK_PCHCTRL_CHEN;
(gdb) 
0x00000ea4	371		GCLK->PCHCTRL[channel].reg &= ~GCLK_PCHCTRL_CHEN;
(gdb) 
0x00000ea6	371		GCLK->PCHCTRL[channel].reg &= ~GCLK_PCHCTRL_CHEN;
(gdb) 
0x00000ea8	371		GCLK->PCHCTRL[channel].reg &= ~GCLK_PCHCTRL_CHEN;
(gdb) 
0x00000eaa	371		GCLK->PCHCTRL[channel].reg &= ~GCLK_PCHCTRL_CHEN;
(gdb) 
373		while (GCLK->PCHCTRL[channel].reg & GCLK_PCHCTRL_CHEN) {
(gdb) 
0x00000eae	373		while (GCLK->PCHCTRL[channel].reg & GCLK_PCHCTRL_CHEN) {
(gdb) 
0x00000eb0	373		while (GCLK->PCHCTRL[channel].reg & GCLK_PCHCTRL_CHEN) {
(gdb) 
0x00000eb2	373		while (GCLK->PCHCTRL[channel].reg & GCLK_PCHCTRL_CHEN) {
(gdb) 
0x00000eb4	373		while (GCLK->PCHCTRL[channel].reg & GCLK_PCHCTRL_CHEN) {
(gdb) 
system_interrupt_leave_critical_section ()
    at ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:182
182		cpu_irq_leave_critical();
(gdb) 
0x00000eb8	182		cpu_irq_leave_critical();
(gdb) 
cpu_irq_leave_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:78
78		cpu_irq_critical_section_counter--;
(gdb) 
0x00000156	78		cpu_irq_critical_section_counter--;
(gdb) 
0x00000158	78		cpu_irq_critical_section_counter--;
(gdb) 
0x0000015a	78		cpu_irq_critical_section_counter--;
(gdb) 
82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x0000015e	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000160	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000162	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000164	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000166	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000168	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
83			cpu_irq_enable();
(gdb) 
0x0000016c	83			cpu_irq_enable();
(gdb) 
0x0000016e	83			cpu_irq_enable();
(gdb) 
__DMB () at ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h:357
357	  __ASM volatile ("dmb");
(gdb) 
__enable_irq () at ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h:320
320	  __ASM volatile ("cpsie i");
(gdb) 
cpu_irq_leave_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:85
85	}
(gdb) 
system_gclk_chan_disable (channel=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:378
378	}
(gdb) 
system_gclk_chan_set_config (channel=, config=0x2000204c)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:326
326		GCLK->PCHCTRL[channel].reg = GCLK_PCHCTRL_GEN(config->source_generator);
(gdb) 
0x00000ed4	326		GCLK->PCHCTRL[channel].reg = GCLK_PCHCTRL_GEN(config->source_generator);
(gdb) 
0x00000ed6	326		GCLK->PCHCTRL[channel].reg = GCLK_PCHCTRL_GEN(config->source_generator);
(gdb) 
0x00000ed8	326		GCLK->PCHCTRL[channel].reg = GCLK_PCHCTRL_GEN(config->source_generator);
(gdb) 
0x00000eda	326		GCLK->PCHCTRL[channel].reg = GCLK_PCHCTRL_GEN(config->source_generator);
(gdb) 
0x00000edc	326		GCLK->PCHCTRL[channel].reg = GCLK_PCHCTRL_GEN(config->source_generator);
(gdb) 
0x00000ede	326		GCLK->PCHCTRL[channel].reg = GCLK_PCHCTRL_GEN(config->source_generator);
(gdb) 
329	}
(gdb) 
i2c_master_init (module=0x2000008c , hw=0x42000800, config=0x20002068)
    at ../src/ASF/sam0/drivers/sercom/i2c/i2c_samd21_r21_d10_d11_l21/i2c_master.c:257
257		system_gclk_chan_enable(gclk_index);
(gdb) 
0x00000216	257		system_gclk_chan_enable(gclk_index);
(gdb) 
0x00000218	257		system_gclk_chan_enable(gclk_index);
(gdb) 
system_gclk_chan_enable (channel=20 '24') at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:341
341	{
(gdb) 
0x00000e62	341	{
(gdb) 
system_interrupt_enter_critical_section ()
    at ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:169
169		cpu_irq_enter_critical();
(gdb) 
0x00000e66	169		cpu_irq_enter_critical();
(gdb) 
cpu_irq_enter_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:59
59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
0x00000116	59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
0x00000118	59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
0x0000011a	59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
__get_PRIMASK () at ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h:471
471	  __ASM volatile ("MRS %0, primask" : "=r" (result) );
(gdb) 
cpu_irq_enter_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:60
60			if (cpu_irq_is_enabled()) {
(gdb) 
0x00000122	60			if (cpu_irq_is_enabled()) {
(gdb) 
__disable_irq () at ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h:331
331	  __ASM volatile ("cpsid i");
(gdb) 
__DMB () at ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h:357
357	  __ASM volatile ("dmb");
(gdb) 
cpu_irq_enter_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:61
61				cpu_irq_disable();
(gdb) 
0x0000012c	61				cpu_irq_disable();
(gdb) 
0x0000012e	61				cpu_irq_disable();
(gdb) 
62				cpu_irq_prev_interrupt_state = true;
(gdb) 
0x00000132	62				cpu_irq_prev_interrupt_state = true;
(gdb) 
0x00000134	62				cpu_irq_prev_interrupt_state = true;
(gdb) 
0x00000136	62				cpu_irq_prev_interrupt_state = true;
(gdb) 
70		cpu_irq_critical_section_counter++;
(gdb) 
0x00000140	70		cpu_irq_critical_section_counter++;
(gdb) 
0x00000142	70		cpu_irq_critical_section_counter++;
(gdb) 
0x00000144	70		cpu_irq_critical_section_counter++;
(gdb) 
71	}
(gdb) 
0x00000e68 in system_interrupt_enter_critical_section ()
    at ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:169
169		cpu_irq_enter_critical();
(gdb) 
0x00000e6a	169		cpu_irq_enter_critical();
(gdb) 
0x00000e6c	169		cpu_irq_enter_critical();
(gdb) 
system_gclk_chan_enable (channel=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:345
345		GCLK->PCHCTRL[channel].reg |= GCLK_PCHCTRL_CHEN;
(gdb) 
0x00000e70	345		GCLK->PCHCTRL[channel].reg |= GCLK_PCHCTRL_CHEN;
(gdb) 
0x00000e72	345		GCLK->PCHCTRL[channel].reg |= GCLK_PCHCTRL_CHEN;
(gdb) 
0x00000e74	345		GCLK->PCHCTRL[channel].reg |= GCLK_PCHCTRL_CHEN;
(gdb) 
0x00000e76	345		GCLK->PCHCTRL[channel].reg |= GCLK_PCHCTRL_CHEN;
(gdb) 
347		while (!(GCLK->PCHCTRL[channel].reg & GCLK_PCHCTRL_CHEN)) {
(gdb) 
0x00000e7a	347		while (!(GCLK->PCHCTRL[channel].reg & GCLK_PCHCTRL_CHEN)) {
(gdb) 
0x00000e7c	347		while (!(GCLK->PCHCTRL[channel].reg & GCLK_PCHCTRL_CHEN)) {
(gdb) 
0x00000e7e	347		while (!(GCLK->PCHCTRL[channel].reg & GCLK_PCHCTRL_CHEN)) {
(gdb) 
0x00000e80	347		while (!(GCLK->PCHCTRL[channel].reg & GCLK_PCHCTRL_CHEN)) {
(gdb) 
system_interrupt_leave_critical_section ()
    at ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:182
182		cpu_irq_leave_critical();
(gdb) 
0x00000e84	182		cpu_irq_leave_critical();
(gdb) 
cpu_irq_leave_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:78
78		cpu_irq_critical_section_counter--;
(gdb) 
0x00000156	78		cpu_irq_critical_section_counter--;
(gdb) 
0x00000158	78		cpu_irq_critical_section_counter--;
(gdb) 
0x0000015a	78		cpu_irq_critical_section_counter--;
(gdb) 
82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x0000015e	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000160	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000162	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000164	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000166	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000168	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
83			cpu_irq_enable();
(gdb) 
0x0000016c	83			cpu_irq_enable();
(gdb) 
0x0000016e	83			cpu_irq_enable();
(gdb) 
__DMB () at ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h:357
357	  __ASM volatile ("dmb");
(gdb) 
__enable_irq () at ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h:320
320	  __ASM volatile ("cpsie i");
(gdb) 
cpu_irq_leave_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:85
85	}
(gdb) 
system_gclk_chan_enable (channel=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:352
352	}
(gdb) 
i2c_master_init (module=0x2000008c , hw=0x42000800, config=0x20002068)
    at ../src/ASF/sam0/drivers/sercom/i2c/i2c_samd21_r21_d10_d11_l21/i2c_master.c:258
258		sercom_set_gclk_generator(config->generator_source, false);
(gdb) 
0x0000021c	258		sercom_set_gclk_generator(config->generator_source, false);
(gdb) 
0x0000021e	258		sercom_set_gclk_generator(config->generator_source, false);
(gdb) 
0x00000220	258		sercom_set_gclk_generator(config->generator_source, false);
(gdb) 
sercom_set_gclk_generator (generator_source=GCLK_GENERATOR_0, force_change=false)
    at ../src/ASF/sam0/drivers/sercom/sercom.c:205
205	{
(gdb) 
0x00000836	205	{
(gdb) 
0x00000838	205	{
(gdb) 
207		if (!_sercom_config.generator_is_set || force_change) {
(gdb) 
0x0000083c	207		if (!_sercom_config.generator_is_set || force_change) {
(gdb) 
0x0000083e	207		if (!_sercom_config.generator_is_set || force_change) {
(gdb) 
0x00000840	207		if (!_sercom_config.generator_is_set || force_change) {
(gdb) 
211			gclk_chan_conf.source_generator = generator_source;
(gdb) 
0x00000848	211			gclk_chan_conf.source_generator = generator_source;
(gdb) 
212			system_gclk_chan_set_config(SERCOM_GCLK_ID, &gclk_chan_conf);
(gdb) 
0x0000084c	212			system_gclk_chan_set_config(SERCOM_GCLK_ID, &gclk_chan_conf);
(gdb) 
0x0000084e	212			system_gclk_chan_set_config(SERCOM_GCLK_ID, &gclk_chan_conf);
(gdb) 
system_gclk_chan_set_config (channel=17 '21', config=0x2000203c)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:318
318	{
(gdb) 
0x00000eca	318	{
(gdb) 
0x00000ecc	318	{
(gdb) 
323		system_gclk_chan_disable(channel);
(gdb) 
0x00000ed0	323		system_gclk_chan_disable(channel);
(gdb) 
system_gclk_chan_disable (channel=17 '21')
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:364
364	{
(gdb) 
0x00000e96	364	{
(gdb) 
system_interrupt_enter_critical_section ()
    at ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:169
169		cpu_irq_enter_critical();
(gdb) 
0x00000e9a	169		cpu_irq_enter_critical();
(gdb) 
cpu_irq_enter_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:59
59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
0x00000116	59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
0x00000118	59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
0x0000011a	59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
__get_PRIMASK () at ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h:471
471	  __ASM volatile ("MRS %0, primask" : "=r" (result) );
(gdb) 
cpu_irq_enter_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:60
60			if (cpu_irq_is_enabled()) {
(gdb) 
0x00000122	60			if (cpu_irq_is_enabled()) {
(gdb) 
__disable_irq () at ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h:331
331	  __ASM volatile ("cpsid i");
(gdb) 
__DMB () at ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h:357
357	  __ASM volatile ("dmb");
(gdb) 
cpu_irq_enter_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:61
61				cpu_irq_disable();
(gdb) 
0x0000012c	61				cpu_irq_disable();
(gdb) 
0x0000012e	61				cpu_irq_disable();
(gdb) 
62				cpu_irq_prev_interrupt_state = true;
(gdb) 
0x00000132	62				cpu_irq_prev_interrupt_state = true;
(gdb) 
0x00000134	62				cpu_irq_prev_interrupt_state = true;
(gdb) 
0x00000136	62				cpu_irq_prev_interrupt_state = true;
(gdb) 
70		cpu_irq_critical_section_counter++;
(gdb) 
0x00000140	70		cpu_irq_critical_section_counter++;
(gdb) 
0x00000142	70		cpu_irq_critical_section_counter++;
(gdb) 
0x00000144	70		cpu_irq_critical_section_counter++;
(gdb) 
71	}
(gdb) 
0x00000e9c in system_interrupt_enter_critical_section ()
    at ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:169
169		cpu_irq_enter_critical();
(gdb) 
0x00000e9e	169		cpu_irq_enter_critical();
(gdb) 
0x00000ea0	169		cpu_irq_enter_critical();
(gdb) 
system_gclk_chan_disable (channel=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:371
371		GCLK->PCHCTRL[channel].reg &= ~GCLK_PCHCTRL_CHEN;
(gdb) 
0x00000ea4	371		GCLK->PCHCTRL[channel].reg &= ~GCLK_PCHCTRL_CHEN;
(gdb) 
0x00000ea6	371		GCLK->PCHCTRL[channel].reg &= ~GCLK_PCHCTRL_CHEN;
(gdb) 
0x00000ea8	371		GCLK->PCHCTRL[channel].reg &= ~GCLK_PCHCTRL_CHEN;
(gdb) 
0x00000eaa	371		GCLK->PCHCTRL[channel].reg &= ~GCLK_PCHCTRL_CHEN;
(gdb) 
373		while (GCLK->PCHCTRL[channel].reg & GCLK_PCHCTRL_CHEN) {
(gdb) 
0x00000eae	373		while (GCLK->PCHCTRL[channel].reg & GCLK_PCHCTRL_CHEN) {
(gdb) 
0x00000eb0	373		while (GCLK->PCHCTRL[channel].reg & GCLK_PCHCTRL_CHEN) {
(gdb) 
0x00000eb2	373		while (GCLK->PCHCTRL[channel].reg & GCLK_PCHCTRL_CHEN) {
(gdb) 
0x00000eb4	373		while (GCLK->PCHCTRL[channel].reg & GCLK_PCHCTRL_CHEN) {
(gdb) 
system_interrupt_leave_critical_section ()
    at ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:182
182		cpu_irq_leave_critical();
(gdb) 
0x00000eb8	182		cpu_irq_leave_critical();
(gdb) 
cpu_irq_leave_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:78
78		cpu_irq_critical_section_counter--;
(gdb) 
0x00000156	78		cpu_irq_critical_section_counter--;
(gdb) 
0x00000158	78		cpu_irq_critical_section_counter--;
(gdb) 
0x0000015a	78		cpu_irq_critical_section_counter--;
(gdb) 
82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x0000015e	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000160	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000162	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000164	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000166	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000168	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
83			cpu_irq_enable();
(gdb) 
0x0000016c	83			cpu_irq_enable();
(gdb) 
0x0000016e	83			cpu_irq_enable();
(gdb) 
__DMB () at ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h:357
357	  __ASM volatile ("dmb");
(gdb) 
__enable_irq () at ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h:320
320	  __ASM volatile ("cpsie i");
(gdb) 
cpu_irq_leave_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:85
85	}
(gdb) 
system_gclk_chan_disable (channel=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:378
378	}
(gdb) 
system_gclk_chan_set_config (channel=, config=0x2000203c)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:326
326		GCLK->PCHCTRL[channel].reg = GCLK_PCHCTRL_GEN(config->source_generator);
(gdb) 
0x00000ed4	326		GCLK->PCHCTRL[channel].reg = GCLK_PCHCTRL_GEN(config->source_generator);
(gdb) 
0x00000ed6	326		GCLK->PCHCTRL[channel].reg = GCLK_PCHCTRL_GEN(config->source_generator);
(gdb) 
0x00000ed8	326		GCLK->PCHCTRL[channel].reg = GCLK_PCHCTRL_GEN(config->source_generator);
(gdb) 
0x00000eda	326		GCLK->PCHCTRL[channel].reg = GCLK_PCHCTRL_GEN(config->source_generator);
(gdb) 
0x00000edc	326		GCLK->PCHCTRL[channel].reg = GCLK_PCHCTRL_GEN(config->source_generator);
(gdb) 
0x00000ede	326		GCLK->PCHCTRL[channel].reg = GCLK_PCHCTRL_GEN(config->source_generator);
(gdb) 
329	}
(gdb) 
sercom_set_gclk_generator (generator_source=, force_change=)
    at ../src/ASF/sam0/drivers/sercom/sercom.c:213
213			system_gclk_chan_enable(SERCOM_GCLK_ID);
(gdb) 
0x00000852	213			system_gclk_chan_enable(SERCOM_GCLK_ID);
(gdb) 
0x00000854	213			system_gclk_chan_enable(SERCOM_GCLK_ID);
(gdb) 
system_gclk_chan_enable (channel=17 '21') at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:341
341	{
(gdb) 
0x00000e62	341	{
(gdb) 
system_interrupt_enter_critical_section ()
    at ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:169
169		cpu_irq_enter_critical();
(gdb) 
0x00000e66	169		cpu_irq_enter_critical();
(gdb) 
cpu_irq_enter_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:59
59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
0x00000116	59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
0x00000118	59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
0x0000011a	59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
__get_PRIMASK () at ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h:471
471	  __ASM volatile ("MRS %0, primask" : "=r" (result) );
(gdb) 
cpu_irq_enter_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:60
60			if (cpu_irq_is_enabled()) {
(gdb) 
0x00000122	60			if (cpu_irq_is_enabled()) {
(gdb) 
__disable_irq () at ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h:331
331	  __ASM volatile ("cpsid i");
(gdb) 
__DMB () at ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h:357
357	  __ASM volatile ("dmb");
(gdb) 
cpu_irq_enter_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:61
61				cpu_irq_disable();
(gdb) 
0x0000012c	61				cpu_irq_disable();
(gdb) 
0x0000012e	61				cpu_irq_disable();
(gdb) 
62				cpu_irq_prev_interrupt_state = true;
(gdb) 
0x00000132	62				cpu_irq_prev_interrupt_state = true;
(gdb) 
0x00000134	62				cpu_irq_prev_interrupt_state = true;
(gdb) 
0x00000136	62				cpu_irq_prev_interrupt_state = true;
(gdb) 
70		cpu_irq_critical_section_counter++;
(gdb) 
0x00000140	70		cpu_irq_critical_section_counter++;
(gdb) 
0x00000142	70		cpu_irq_critical_section_counter++;
(gdb) 
0x00000144	70		cpu_irq_critical_section_counter++;
(gdb) 
71	}
(gdb) 
0x00000e68 in system_interrupt_enter_critical_section ()
    at ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:169
169		cpu_irq_enter_critical();
(gdb) 
0x00000e6a	169		cpu_irq_enter_critical();
(gdb) 
0x00000e6c	169		cpu_irq_enter_critical();
(gdb) 
system_gclk_chan_enable (channel=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:345
345		GCLK->PCHCTRL[channel].reg |= GCLK_PCHCTRL_CHEN;
(gdb) 
0x00000e70	345		GCLK->PCHCTRL[channel].reg |= GCLK_PCHCTRL_CHEN;
(gdb) 
0x00000e72	345		GCLK->PCHCTRL[channel].reg |= GCLK_PCHCTRL_CHEN;
(gdb) 
0x00000e74	345		GCLK->PCHCTRL[channel].reg |= GCLK_PCHCTRL_CHEN;
(gdb) 
0x00000e76	345		GCLK->PCHCTRL[channel].reg |= GCLK_PCHCTRL_CHEN;
(gdb) 
347		while (!(GCLK->PCHCTRL[channel].reg & GCLK_PCHCTRL_CHEN)) {
(gdb) 
0x00000e7a	347		while (!(GCLK->PCHCTRL[channel].reg & GCLK_PCHCTRL_CHEN)) {
(gdb) 
0x00000e7c	347		while (!(GCLK->PCHCTRL[channel].reg & GCLK_PCHCTRL_CHEN)) {
(gdb) 
0x00000e7e	347		while (!(GCLK->PCHCTRL[channel].reg & GCLK_PCHCTRL_CHEN)) {
(gdb) 
0x00000e80	347		while (!(GCLK->PCHCTRL[channel].reg & GCLK_PCHCTRL_CHEN)) {
(gdb) 
system_interrupt_leave_critical_section ()
    at ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:182
182		cpu_irq_leave_critical();
(gdb) 
0x00000e84	182		cpu_irq_leave_critical();
(gdb) 
cpu_irq_leave_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:78
78		cpu_irq_critical_section_counter--;
(gdb) 
0x00000156	78		cpu_irq_critical_section_counter--;
(gdb) 
0x00000158	78		cpu_irq_critical_section_counter--;
(gdb) 
0x0000015a	78		cpu_irq_critical_section_counter--;
(gdb) 
82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x0000015e	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000160	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000162	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000164	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000166	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000168	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
83			cpu_irq_enable();
(gdb) 
0x0000016c	83			cpu_irq_enable();
(gdb) 
0x0000016e	83			cpu_irq_enable();
(gdb) 
__DMB () at ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h:357
357	  __ASM volatile ("dmb");
(gdb) 
__enable_irq () at ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h:320
320	  __ASM volatile ("cpsie i");
(gdb) 
cpu_irq_leave_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:85
85	}
(gdb) 
system_gclk_chan_enable (channel=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:352
352	}
(gdb) 
sercom_set_gclk_generator (generator_source=, force_change=)
    at ../src/ASF/sam0/drivers/sercom/sercom.c:216
216			_sercom_config.generator_source = generator_source;
(gdb) 
0x00000858	216			_sercom_config.generator_source = generator_source;
(gdb) 
217			_sercom_config.generator_is_set = true;
(gdb) 
0x0000085c	217			_sercom_config.generator_is_set = true;
(gdb) 
219			return STATUS_OK;
(gdb) 
0x00000860	219			return STATUS_OK;
(gdb) 
227	}
(gdb) 
Cannot access memory at address 0x123b4246
0x00000874 in sercom_set_gclk_generator (generator_source=, force_change=)
    at ../src/ASF/sam0/drivers/sercom/sercom.c:227
227	}
(gdb) 
i2c_master_init (module=0x2000008c , hw=0x42000800, config=0x20002068)
    at ../src/ASF/sam0/drivers/sercom/i2c/i2c_samd21_r21_d10_d11_l21/i2c_master.c:261
261		if (i2c_module->CTRLA.reg & SERCOM_I2CM_CTRLA_ENABLE) {
(gdb) 
262			return STATUS_ERR_DENIED;
(gdb) 
261		if (i2c_module->CTRLA.reg & SERCOM_I2CM_CTRLA_ENABLE) {
(gdb) 
0x00000228	261		if (i2c_module->CTRLA.reg & SERCOM_I2CM_CTRLA_ENABLE) {
(gdb) 
266		if (i2c_module->CTRLA.reg & SERCOM_I2CM_CTRLA_SWRST) {
(gdb) 
267			return STATUS_BUSY;
(gdb) 
266		if (i2c_module->CTRLA.reg & SERCOM_I2CM_CTRLA_SWRST) {
(gdb) 
0x00000232	266		if (i2c_module->CTRLA.reg & SERCOM_I2CM_CTRLA_SWRST) {
(gdb) 
272		uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw);
(gdb) 
0x00000238	272		uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw);
(gdb) 
0x0000023a	272		uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw);
(gdb) 
0x0000023c	272		uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw);
(gdb) 
_sercom_get_sercom_inst_index (sercom_instance=0x42000800) at ../src/ASF/sam0/drivers/sercom/sercom.c:282
282	{
(gdb) 
0x00000a0a	282	{
(gdb) 
284		Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
(gdb) 
0x00000a0e	284		Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
(gdb) 
0x00000a10	284		Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
(gdb) 
0x00000a12	284		Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
(gdb) 
0x00000a14	284		Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
(gdb) 
0x00000a16	284		Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
(gdb) 
288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
0x00000a1a	288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
0x00000a1c	288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
287		for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
(gdb) 
0x00000a20	287		for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
(gdb) 
288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
0x00000a24	288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
0x00000a26	288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
0x00000a28	288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
287		for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
(gdb) 
0x00000a34	287		for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
(gdb) 
0x00000a36	287		for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
(gdb) 
0x00000a20	287		for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
(gdb) 
288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
0x00000a24	288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
0x00000a26	288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
0x00000a28	288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
0x00000a2a	288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
289				return i;
(gdb) 
0x00000a30	289				return i;
(gdb) 
296	}
(gdb) 
0x00000a3c in _sercom_get_sercom_inst_index (sercom_instance=)
    at ../src/ASF/sam0/drivers/sercom/sercom.c:296
296	}
(gdb) 
0x0000023e in i2c_master_init (module=0x2000008c , hw=0x42000800, config=0x20002068)
    at ../src/ASF/sam0/drivers/sercom/i2c/i2c_samd21_r21_d10_d11_l21/i2c_master.c:272
272		uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw);
(gdb) 
273		_sercom_set_handler(instance_index, _i2c_master_interrupt_handler);
(gdb) 
0x00000242	273		_sercom_set_handler(instance_index, _i2c_master_interrupt_handler);
(gdb) 
0x00000244	273		_sercom_set_handler(instance_index, _i2c_master_interrupt_handler);
(gdb) 
_sercom_set_handler (instance=2 '02', interrupt_handler=0x671 )
    at ../src/ASF/sam0/drivers/sercom/sercom_interrupt.c:78
78	{
(gdb) 
80		if (_handler_table_initialized == false) {
(gdb) 
0x00000a4c	80		if (_handler_table_initialized == false) {
(gdb) 
0x00000a4e	80		if (_handler_table_initialized == false) {
(gdb) 
0x00000a50	80		if (_handler_table_initialized == false) {
(gdb) 
82				_sercom_interrupt_handlers[i] = &_sercom_default_handler;
(gdb) 
0x00000a54	82				_sercom_interrupt_handlers[i] = &_sercom_default_handler;
(gdb) 
83				_sercom_instances[i] = NULL;
(gdb) 
0x00000a58	83				_sercom_instances[i] = NULL;
(gdb) 
82				_sercom_interrupt_handlers[i] = &_sercom_default_handler;
(gdb) 
83				_sercom_instances[i] = NULL;
(gdb) 
0x00000a5e	83				_sercom_instances[i] = NULL;
(gdb) 
0x00000a60	83				_sercom_instances[i] = NULL;
(gdb) 
81			for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
(gdb) 
0x00000a64	81			for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
(gdb) 
82				_sercom_interrupt_handlers[i] = &_sercom_default_handler;
(gdb) 
83				_sercom_instances[i] = NULL;
(gdb) 
0x00000a5e	83				_sercom_instances[i] = NULL;
(gdb) 
0x00000a60	83				_sercom_instances[i] = NULL;
(gdb) 
81			for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
(gdb) 
0x00000a64	81			for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
(gdb) 
82				_sercom_interrupt_handlers[i] = &_sercom_default_handler;
(gdb) 
83				_sercom_instances[i] = NULL;
(gdb) 
0x00000a5e	83				_sercom_instances[i] = NULL;
(gdb) 
0x00000a60	83				_sercom_instances[i] = NULL;
(gdb) 
81			for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
(gdb) 
0x00000a64	81			for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
(gdb) 
82				_sercom_interrupt_handlers[i] = &_sercom_default_handler;
(gdb) 
83				_sercom_instances[i] = NULL;
(gdb) 
0x00000a5e	83				_sercom_instances[i] = NULL;
(gdb) 
0x00000a60	83				_sercom_instances[i] = NULL;
(gdb) 
81			for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
(gdb) 
0x00000a64	81			for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
(gdb) 
82				_sercom_interrupt_handlers[i] = &_sercom_default_handler;
(gdb) 
83				_sercom_instances[i] = NULL;
(gdb) 
0x00000a5e	83				_sercom_instances[i] = NULL;
(gdb) 
0x00000a60	83				_sercom_instances[i] = NULL;
(gdb) 
81			for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
(gdb) 
0x00000a64	81			for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
(gdb) 
82				_sercom_interrupt_handlers[i] = &_sercom_default_handler;
(gdb) 
83				_sercom_instances[i] = NULL;
(gdb) 
0x00000a5e	83				_sercom_instances[i] = NULL;
(gdb) 
0x00000a60	83				_sercom_instances[i] = NULL;
(gdb) 
81			for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
(gdb) 
0x00000a64	81			for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
(gdb) 
86			_handler_table_initialized = true;
(gdb) 
0x00000a68	86			_handler_table_initialized = true;
(gdb) 
0x00000a6a	86			_handler_table_initialized = true;
(gdb) 
90		_sercom_interrupt_handlers[instance] = interrupt_handler;
(gdb) 
0x00000a6e	90		_sercom_interrupt_handlers[instance] = interrupt_handler;
(gdb) 
0x00000a70	90		_sercom_interrupt_handlers[instance] = interrupt_handler;
(gdb) 
91	}
(gdb) 
i2c_master_init (module=0x2000008c , hw=0x42000800, config=0x20002068)
    at ../src/ASF/sam0/drivers/sercom/i2c/i2c_samd21_r21_d10_d11_l21/i2c_master.c:274
274		_sercom_instances[instance_index] = module;
(gdb) 
0x00000248	274		_sercom_instances[instance_index] = module;
(gdb) 
0x0000024a	274		_sercom_instances[instance_index] = module;
(gdb) 
277		module->registered_callback = 0;
(gdb) 
0x0000024e	277		module->registered_callback = 0;
(gdb) 
278		module->enabled_callback = 0;
(gdb) 
279		module->buffer_length = 0;
(gdb) 
0x00000254	279		module->buffer_length = 0;
(gdb) 
280		module->buffer_remaining = 0;
(gdb) 
282		module->status = STATUS_OK;
(gdb) 
0x0000025a	282		module->status = STATUS_OK;
(gdb) 
283		module->buffer = NULL;
(gdb) 
287		i2c_module->CTRLA.reg = SERCOM_I2CM_CTRLA_MODE(0x5);
(gdb) 
0x00000260	287		i2c_module->CTRLA.reg = SERCOM_I2CM_CTRLA_MODE(0x5);
(gdb) 
_i2c_master_set_config (config=0x20002068, module=0x2000008c )
    at ../src/ASF/sam0/drivers/sercom/i2c/i2c_samd21_r21_d10_d11_l21/i2c_master.c:94
94		SercomI2cm *const i2c_module = &(module->hw->I2CM);
(gdb) 
97		uint8_t sercom_index = _sercom_get_sercom_inst_index(sercom_hw);
(gdb) 
0x00000266	97		uint8_t sercom_index = _sercom_get_sercom_inst_index(sercom_hw);
(gdb) 
_sercom_get_sercom_inst_index (sercom_instance=0x42000800) at ../src/ASF/sam0/drivers/sercom/sercom.c:282
282	{
(gdb) 
0x00000a0a	282	{
(gdb) 
284		Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
(gdb) 
0x00000a0e	284		Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
(gdb) 
0x00000a10	284		Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
(gdb) 
0x00000a12	284		Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
(gdb) 
0x00000a14	284		Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
(gdb) 
0x00000a16	284		Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
(gdb) 
288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
0x00000a1a	288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
0x00000a1c	288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
287		for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
(gdb) 
0x00000a20	287		for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
(gdb) 
288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
0x00000a24	288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
0x00000a26	288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
0x00000a28	288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
287		for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
(gdb) 
0x00000a34	287		for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
(gdb) 
0x00000a36	287		for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
(gdb) 
0x00000a20	287		for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
(gdb) 
288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
0x00000a24	288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
0x00000a26	288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
0x00000a28	288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
0x00000a2a	288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
289				return i;
(gdb) 
0x00000a30	289				return i;
(gdb) 
296	}
(gdb) 
0x00000a3c in _sercom_get_sercom_inst_index (sercom_instance=)
    at ../src/ASF/sam0/drivers/sercom/sercom.c:296
296	}
(gdb) 
0x00000268 in _i2c_master_set_config (config=0x20002068, module=0x2000008c )
    at ../src/ASF/sam0/drivers/sercom/i2c/i2c_samd21_r21_d10_d11_l21/i2c_master.c:97
97		uint8_t sercom_index = _sercom_get_sercom_inst_index(sercom_hw);
(gdb) 
system_pinmux_get_config_defaults (config=0x20002048) at ../src/ASF/sam0/drivers/system/pinmux/pinmux.h:311
311		config->mux_position = SYSTEM_PINMUX_GPIO;
(gdb) 
0x0000026c	311		config->mux_position = SYSTEM_PINMUX_GPIO;
(gdb) 
0x0000026e	311		config->mux_position = SYSTEM_PINMUX_GPIO;
(gdb) 
312		config->direction    = SYSTEM_PINMUX_PIN_DIR_INPUT;
(gdb) 
313		config->input_pull   = SYSTEM_PINMUX_PIN_PULL_UP;
(gdb) 
0x00000274	313		config->input_pull   = SYSTEM_PINMUX_PIN_PULL_UP;
(gdb) 
314		config->powersave    = false;
(gdb) 
_i2c_master_set_config (config=0x20002068, module=0x2000008c )
    at ../src/ASF/sam0/drivers/sercom/i2c/i2c_samd21_r21_d10_d11_l21/i2c_master.c:103
103		uint32_t pad0 = config->pinmux_pad0;
(gdb) 
104		uint32_t pad1 = config->pinmux_pad1;
(gdb) 
107		if (pad0 == PINMUX_DEFAULT) {
(gdb) 
0x0000027e	107		if (pad0 == PINMUX_DEFAULT) {
(gdb) 
108			pad0 = _sercom_get_default_pad(sercom_hw, 0);
(gdb) 
0x00000282	108			pad0 = _sercom_get_default_pad(sercom_hw, 0);
(gdb) 
0x00000284	108			pad0 = _sercom_get_default_pad(sercom_hw, 0);
(gdb) 
0x00000286	108			pad0 = _sercom_get_default_pad(sercom_hw, 0);
(gdb) 
_sercom_get_default_pad (sercom_module=0x42000800, pad=0 '00')
    at ../src/ASF/sam0/drivers/sercom/sercom.c:263
263		switch ((uintptr_t)sercom_module) {
(gdb) 
0x00000886	263		switch ((uintptr_t)sercom_module) {
(gdb) 
0x00000888	263		switch ((uintptr_t)sercom_module) {
(gdb) 
0x000008f4	265			MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
(gdb) 
0x000008f6	265			MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
(gdb) 
0x000008f8	265			MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
(gdb) 
0x000008fa	265			MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
(gdb) 
0x00000906	265			MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
(gdb) 
0x00000908	265			MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
(gdb) 
270	}
(gdb) 
_i2c_master_set_config (config=0x20002068, module=0x2000008c )
    at ../src/ASF/sam0/drivers/sercom/i2c/i2c_samd21_r21_d10_d11_l21/i2c_master.c:110
110		pin_conf.mux_position = pad0 & 0xFFFF;
(gdb) 
0x0000028a	110		pin_conf.mux_position = pad0 & 0xFFFF;
(gdb) 
111		pin_conf.direction    = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK;
(gdb) 
0x0000028e	111		pin_conf.direction    = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK;
(gdb) 
112		system_pinmux_pin_set_config(pad0 >> 16, &pin_conf);
(gdb) 
0x00000292	112		system_pinmux_pin_set_config(pad0 >> 16, &pin_conf);
(gdb) 
0x00000294	112		system_pinmux_pin_set_config(pad0 >> 16, &pin_conf);
(gdb) 
0x00000296	112		system_pinmux_pin_set_config(pad0 >> 16, &pin_conf);
(gdb) 
0x00000298	112		system_pinmux_pin_set_config(pad0 >> 16, &pin_conf);
(gdb) 
system_pinmux_pin_set_config (gpio_pin=8 '\b', config=0x20002048)
    at ../src/ASF/sam0/drivers/system/pinmux/pinmux.c:163
163	{
(gdb) 
0x00000faa	163	{
(gdb) 
0x00000fac	163	{
(gdb) 
system_pinmux_get_group_from_gpio_pin (gpio_pin=8 '\b')
    at ../src/ASF/sam0/drivers/system/pinmux/pinmux.h:351
351		if (port_index < PORT_INST_NUM) {
(gdb) 
355			return NULL;
(gdb) 
351		if (port_index < PORT_INST_NUM) {
(gdb) 
0x00000fb4	351		if (port_index Group[group_index]);
(gdb) 
0x00000fb8	352			return &(ports[port_index]->Group[group_index]);
(gdb) 
0x00000fba	352			return &(ports[port_index]->Group[group_index]);
(gdb) 
0x00000fbc	352			return &(ports[port_index]->Group[group_index]);
(gdb) 
system_pinmux_pin_set_config (gpio_pin=, config=0x20002048)
    at ../src/ASF/sam0/drivers/system/pinmux/pinmux.c:165
165		uint32_t pin_mask = (1UL << (gpio_pin % 32));
(gdb) 
0x00000fc0	165		uint32_t pin_mask = (1UL << (gpio_pin % 32));
(gdb) 
0x00000fc2	165		uint32_t pin_mask = (1UL << (gpio_pin % 32));
(gdb) 
0x00000fc4	165		uint32_t pin_mask = (1UL <powersave) {
(gdb) 
0x00000f20	72		if (!config->powersave) {
(gdb) 
0x00000f22	72		if (!config->powersave) {
(gdb) 
75			if (config->mux_position != SYSTEM_PINMUX_GPIO) {
(gdb) 
0x00000f26	75			if (config->mux_position != SYSTEM_PINMUX_GPIO) {
(gdb) 
0x00000f28	75			if (config->mux_position != SYSTEM_PINMUX_GPIO) {
(gdb) 
77				pin_cfg |= (config->mux_position <mux_position <mux_position <mux_position <mux_position <direction == SYSTEM_PINMUX_PIN_DIR_INPUT) ||
(gdb) 
0x00000f38	81			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_INPUT) ||
(gdb) 
0x00000f3a	81			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_INPUT) ||
(gdb) 
0x00000f3c	81			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_INPUT) ||
(gdb) 
87				if (config->input_pull != SYSTEM_PINMUX_PIN_PULL_NONE) {
(gdb) 
0x00000f40	87				if (config->input_pull != SYSTEM_PINMUX_PIN_PULL_NONE) {
(gdb) 
0x00000f42	87				if (config->input_pull != SYSTEM_PINMUX_PIN_PULL_NONE) {
(gdb) 
88					pin_cfg |= PORT_WRCONFIG_PULLEN;
(gdb) 
0x00000f4e	88					pin_cfg |= PORT_WRCONFIG_PULLEN;
(gdb) 
0x00000f50	88					pin_cfg |= PORT_WRCONFIG_PULLEN;
(gdb) 
92				port->DIRCLR.reg = pin_mask;
(gdb) 
96			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
(gdb) 
0x00000f56	96			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
(gdb) 
0x00000f58	96			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
(gdb) 
0x00000f5a	96			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
(gdb) 
101				pin_cfg &= ~PORT_WRCONFIG_PULLEN;
(gdb) 
0x00000f5e	101				pin_cfg &= ~PORT_WRCONFIG_PULLEN;
(gdb) 
0x00000f60	101				pin_cfg &= ~PORT_WRCONFIG_PULLEN;
(gdb) 
109		uint32_t lower_pin_mask = (pin_mask & 0xFFFF);
(gdb) 
0x00000f68	109		uint32_t lower_pin_mask = (pin_mask & 0xFFFF);
(gdb) 
115			= (lower_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
(gdb) 
0x00000f6c	115			= (lower_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
(gdb) 
0x00000f6e	115			= (lower_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
(gdb) 
116				pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG;
(gdb) 
115			= (lower_pin_mask <> 16);
(gdb) 
121			= (upper_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
(gdb) 
0x00000f78	121			= (upper_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
(gdb) 
0x00000f7a	121			= (upper_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
(gdb) 
122				pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG |
(gdb) 
121			= (upper_pin_mask <powersave) {
(gdb) 
0x00000f82	125		if(!config->powersave) {
(gdb) 
0x00000f84	125		if(!config->powersave) {
(gdb) 
129			if (pin_cfg & PORT_WRCONFIG_PULLEN) {
(gdb) 
0x00000f88	129			if (pin_cfg & PORT_WRCONFIG_PULLEN) {
(gdb) 
140			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
(gdb) 
0x00000f98	140			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
(gdb) 
0x00000f9a	140			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
(gdb) 
0x00000f9c	140			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
(gdb) 
143				port->DIRSET.reg = pin_mask;
(gdb) 
146	}
(gdb) 
system_pinmux_pin_set_config (gpio_pin=, config=)
    at ../src/ASF/sam0/drivers/system/pinmux/pinmux.c:168
168	}
(gdb) 
_i2c_master_set_config (config=0x20002068, module=0x2000008c )
    at ../src/ASF/sam0/drivers/sercom/i2c/i2c_samd21_r21_d10_d11_l21/i2c_master.c:115
115		if (pad1 == PINMUX_DEFAULT) {
(gdb) 
0x0000029c	115		if (pad1 == PINMUX_DEFAULT) {
(gdb) 
116			pad1 = _sercom_get_default_pad(sercom_hw, 1);
(gdb) 
0x000002a0	116			pad1 = _sercom_get_default_pad(sercom_hw, 1);
(gdb) 
0x000002a2	116			pad1 = _sercom_get_default_pad(sercom_hw, 1);
(gdb) 
0x000002a4	116			pad1 = _sercom_get_default_pad(sercom_hw, 1);
(gdb) 
_sercom_get_default_pad (sercom_module=0x42000800, pad=1 '01')
    at ../src/ASF/sam0/drivers/sercom/sercom.c:263
263		switch ((uintptr_t)sercom_module) {
(gdb) 
0x00000886	263		switch ((uintptr_t)sercom_module) {
(gdb) 
0x00000888	263		switch ((uintptr_t)sercom_module) {
(gdb) 
0x000008f4	265			MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
(gdb) 
0x000008f6	265			MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
(gdb) 
0x00000988	265			MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
(gdb) 
0x0000098a	265			MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
(gdb) 
270	}
(gdb) 
0x000002a6 in _i2c_master_set_config (config=0x20002068, module=0x2000008c )
    at ../src/ASF/sam0/drivers/sercom/i2c/i2c_samd21_r21_d10_d11_l21/i2c_master.c:116
116			pad1 = _sercom_get_default_pad(sercom_hw, 1);
(gdb) 
118		pin_conf.mux_position = pad1 & 0xFFFF;
(gdb) 
0x000002aa	118		pin_conf.mux_position = pad1 & 0xFFFF;
(gdb) 
119		pin_conf.direction    = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK;
(gdb) 
0x000002ae	119		pin_conf.direction    = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK;
(gdb) 
120		system_pinmux_pin_set_config(pad1 >> 16, &pin_conf);
(gdb) 
0x000002b2	120		system_pinmux_pin_set_config(pad1 >> 16, &pin_conf);
(gdb) 
0x000002b4	120		system_pinmux_pin_set_config(pad1 >> 16, &pin_conf);
(gdb) 
0x000002b6	120		system_pinmux_pin_set_config(pad1 >> 16, &pin_conf);
(gdb) 
0x000002b8	120		system_pinmux_pin_set_config(pad1 >> 16, &pin_conf);
(gdb) 
system_pinmux_pin_set_config (gpio_pin=9 '\t', config=0x20002048)
    at ../src/ASF/sam0/drivers/system/pinmux/pinmux.c:163
163	{
(gdb) 
0x00000faa	163	{
(gdb) 
0x00000fac	163	{
(gdb) 
system_pinmux_get_group_from_gpio_pin (gpio_pin=9 '\t')
    at ../src/ASF/sam0/drivers/system/pinmux/pinmux.h:351
351		if (port_index < PORT_INST_NUM) {
(gdb) 
355			return NULL;
(gdb) 
351		if (port_index < PORT_INST_NUM) {
(gdb) 
0x00000fb4	351		if (port_index Group[group_index]);
(gdb) 
0x00000fb8	352			return &(ports[port_index]->Group[group_index]);
(gdb) 
0x00000fba	352			return &(ports[port_index]->Group[group_index]);
(gdb) 
0x00000fbc	352			return &(ports[port_index]->Group[group_index]);
(gdb) 
system_pinmux_pin_set_config (gpio_pin=, config=0x20002048)
    at ../src/ASF/sam0/drivers/system/pinmux/pinmux.c:165
165		uint32_t pin_mask = (1UL << (gpio_pin % 32));
(gdb) 
0x00000fc0	165		uint32_t pin_mask = (1UL << (gpio_pin % 32));
(gdb) 
0x00000fc2	165		uint32_t pin_mask = (1UL << (gpio_pin % 32));
(gdb) 
0x00000fc4	165		uint32_t pin_mask = (1UL <powersave) {
(gdb) 
0x00000f20	72		if (!config->powersave) {
(gdb) 
0x00000f22	72		if (!config->powersave) {
(gdb) 
75			if (config->mux_position != SYSTEM_PINMUX_GPIO) {
(gdb) 
0x00000f26	75			if (config->mux_position != SYSTEM_PINMUX_GPIO) {
(gdb) 
0x00000f28	75			if (config->mux_position != SYSTEM_PINMUX_GPIO) {
(gdb) 
77				pin_cfg |= (config->mux_position <mux_position <mux_position <mux_position <mux_position <direction == SYSTEM_PINMUX_PIN_DIR_INPUT) ||
(gdb) 
0x00000f38	81			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_INPUT) ||
(gdb) 
0x00000f3a	81			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_INPUT) ||
(gdb) 
0x00000f3c	81			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_INPUT) ||
(gdb) 
87				if (config->input_pull != SYSTEM_PINMUX_PIN_PULL_NONE) {
(gdb) 
0x00000f40	87				if (config->input_pull != SYSTEM_PINMUX_PIN_PULL_NONE) {
(gdb) 
0x00000f42	87				if (config->input_pull != SYSTEM_PINMUX_PIN_PULL_NONE) {
(gdb) 
88					pin_cfg |= PORT_WRCONFIG_PULLEN;
(gdb) 
0x00000f4e	88					pin_cfg |= PORT_WRCONFIG_PULLEN;
(gdb) 
0x00000f50	88					pin_cfg |= PORT_WRCONFIG_PULLEN;
(gdb) 
92				port->DIRCLR.reg = pin_mask;
(gdb) 
96			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
(gdb) 
0x00000f56	96			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
(gdb) 
0x00000f58	96			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
(gdb) 
0x00000f5a	96			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
(gdb) 
101				pin_cfg &= ~PORT_WRCONFIG_PULLEN;
(gdb) 
0x00000f5e	101				pin_cfg &= ~PORT_WRCONFIG_PULLEN;
(gdb) 
0x00000f60	101				pin_cfg &= ~PORT_WRCONFIG_PULLEN;
(gdb) 
109		uint32_t lower_pin_mask = (pin_mask & 0xFFFF);
(gdb) 
0x00000f68	109		uint32_t lower_pin_mask = (pin_mask & 0xFFFF);
(gdb) 
115			= (lower_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
(gdb) 
0x00000f6c	115			= (lower_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
(gdb) 
0x00000f6e	115			= (lower_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
(gdb) 
116				pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG;
(gdb) 
115			= (lower_pin_mask <> 16);
(gdb) 
121			= (upper_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
(gdb) 
0x00000f78	121			= (upper_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
(gdb) 
0x00000f7a	121			= (upper_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
(gdb) 
122				pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG |
(gdb) 
121			= (upper_pin_mask <powersave) {
(gdb) 
0x00000f82	125		if(!config->powersave) {
(gdb) 
0x00000f84	125		if(!config->powersave) {
(gdb) 
129			if (pin_cfg & PORT_WRCONFIG_PULLEN) {
(gdb) 
0x00000f88	129			if (pin_cfg & PORT_WRCONFIG_PULLEN) {
(gdb) 
140			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
(gdb) 
0x00000f98	140			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
(gdb) 
0x00000f9a	140			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
(gdb) 
0x00000f9c	140			if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
(gdb) 
143				port->DIRSET.reg = pin_mask;
(gdb) 
146	}
(gdb) 
system_pinmux_pin_set_config (gpio_pin=, config=)
    at ../src/ASF/sam0/drivers/system/pinmux/pinmux.c:168
168	}
(gdb) 
_i2c_master_set_config (config=0x20002068, module=0x2000008c )
    at ../src/ASF/sam0/drivers/sercom/i2c/i2c_samd21_r21_d10_d11_l21/i2c_master.c:123
123		module->unknown_bus_state_timeout = config->unknown_bus_state_timeout;
(gdb) 
0x000002bc	123		module->unknown_bus_state_timeout = config->unknown_bus_state_timeout;
(gdb) 
126		module->buffer_timeout = config->buffer_timeout;
(gdb) 
0x000002c0	126		module->buffer_timeout = config->buffer_timeout;
(gdb) 
129		if (config->run_in_standby || system_is_debugger_present()) {
(gdb) 
130			tmp_ctrla = SERCOM_I2CM_CTRLA_RUNSTDBY;
(gdb) 
129		if (config->run_in_standby || system_is_debugger_present()) {
(gdb) 
0x000002c8	129		if (config->run_in_standby || system_is_debugger_present()) {
(gdb) 
system_is_debugger_present () at ../src/ASF/sam0/drivers/system/system.h:511
511		return DSU->STATUSB.reg & DSU_STATUSB_DBGPRES;
(gdb) 
0x000002cc	511		return DSU->STATUSB.reg & DSU_STATUSB_DBGPRES;
(gdb) 
_i2c_master_set_config (config=0x20002068, module=0x2000008c )
    at ../src/ASF/sam0/drivers/sercom/i2c/i2c_samd21_r21_d10_d11_l21/i2c_master.c:129
129		if (config->run_in_standby || system_is_debugger_present()) {
(gdb) 
132			tmp_ctrla = 0;
(gdb) 
0x000002d2	132			tmp_ctrla = 0;
(gdb) 
136		if (config->start_hold_time != I2C_MASTER_START_HOLD_TIME_DISABLED) {
(gdb) 
0x000002d6	136		if (config->start_hold_time != I2C_MASTER_START_HOLD_TIME_DISABLED) {
(gdb) 
0x000002d8	136		if (config->start_hold_time != I2C_MASTER_START_HOLD_TIME_DISABLED) {
(gdb) 
137			tmp_ctrla |= config->start_hold_time;
(gdb) 
141		tmp_ctrla |= config->transfer_speed;
(gdb) 
0x000002de	141		tmp_ctrla |= config->transfer_speed;
(gdb) 
144		if (config->scl_low_timeout) {
(gdb) 
0x000002e2	144		if (config->scl_low_timeout) {
(gdb) 
0x000002e4	144		if (config->scl_low_timeout) {
(gdb) 
0x000002e6	144		if (config->scl_low_timeout) {
(gdb) 
149		if (config->inactive_timeout != I2C_MASTER_INACTIVE_TIMEOUT_DISABLED) {
(gdb) 
0x000002f0	149		if (config->inactive_timeout != I2C_MASTER_INACTIVE_TIMEOUT_DISABLED) {
(gdb) 
0x000002f2	149		if (config->inactive_timeout != I2C_MASTER_INACTIVE_TIMEOUT_DISABLED) {
(gdb) 
154		if (config->scl_stretch_only_after_ack_bit) {
(gdb) 
0x000002f8	154		if (config->scl_stretch_only_after_ack_bit) {
(gdb) 
0x000002fa	154		if (config->scl_stretch_only_after_ack_bit) {
(gdb) 
0x000002fc	154		if (config->scl_stretch_only_after_ack_bit) {
(gdb) 
159		if (config->slave_scl_low_extend_timeout) {
(gdb) 
0x00000306	159		if (config->slave_scl_low_extend_timeout) {
(gdb) 
0x00000308	159		if (config->slave_scl_low_extend_timeout) {
(gdb) 
0x0000030a	159		if (config->slave_scl_low_extend_timeout) {
(gdb) 
164		if (config->master_scl_low_extend_timeout) {
(gdb) 
0x00000314	164		if (config->master_scl_low_extend_timeout) {
(gdb) 
0x00000316	164		if (config->master_scl_low_extend_timeout) {
(gdb) 
0x00000318	164		if (config->master_scl_low_extend_timeout) {
(gdb) 
169		i2c_module->CTRLA.reg |= tmp_ctrla;
(gdb) 
0x00000322	169		i2c_module->CTRLA.reg |= tmp_ctrla;
(gdb) 
0x00000324	169		i2c_module->CTRLA.reg |= tmp_ctrla;
(gdb) 
172		i2c_module->CTRLB.reg = SERCOM_I2CM_CTRLB_SMEN;
(gdb) 
0x00000328	172		i2c_module->CTRLB.reg = SERCOM_I2CM_CTRLB_SMEN;
(gdb) 
0x0000032a	172		i2c_module->CTRLB.reg = SERCOM_I2CM_CTRLB_SMEN;
(gdb) 
175		tmp_baud = (int32_t)(div_ceil(
(gdb) 
0x0000032e	175		tmp_baud = (int32_t)(div_ceil(
(gdb) 
0x00000330	175		tmp_baud = (int32_t)(div_ceil(
(gdb) 
0x00000332	175		tmp_baud = (int32_t)(div_ceil(
(gdb) 
0x00000334	175		tmp_baud = (int32_t)(div_ceil(
(gdb) 
0x00000336	175		tmp_baud = (int32_t)(div_ceil(
(gdb) 
system_gclk_chan_get_hz (channel=20 '24') at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:454
454	{
(gdb) 
0x00000eee	454	{
(gdb) 
system_interrupt_enter_critical_section ()
    at ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:169
169		cpu_irq_enter_critical();
(gdb) 
0x00000ef2	169		cpu_irq_enter_critical();
(gdb) 
cpu_irq_enter_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:59
59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
0x00000116	59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
0x00000118	59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
0x0000011a	59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
__get_PRIMASK () at ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h:471
471	  __ASM volatile ("MRS %0, primask" : "=r" (result) );
(gdb) 
cpu_irq_enter_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:60
60			if (cpu_irq_is_enabled()) {
(gdb) 
0x00000122	60			if (cpu_irq_is_enabled()) {
(gdb) 
__disable_irq () at ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h:331
331	  __ASM volatile ("cpsid i");
(gdb) 
__DMB () at ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h:357
357	  __ASM volatile ("dmb");
(gdb) 
cpu_irq_enter_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:61
61				cpu_irq_disable();
(gdb) 
0x0000012c	61				cpu_irq_disable();
(gdb) 
0x0000012e	61				cpu_irq_disable();
(gdb) 
62				cpu_irq_prev_interrupt_state = true;
(gdb) 
0x00000132	62				cpu_irq_prev_interrupt_state = true;
(gdb) 
0x00000134	62				cpu_irq_prev_interrupt_state = true;
(gdb) 
0x00000136	62				cpu_irq_prev_interrupt_state = true;
(gdb) 
70		cpu_irq_critical_section_counter++;
(gdb) 
0x00000140	70		cpu_irq_critical_section_counter++;
(gdb) 
0x00000142	70		cpu_irq_critical_section_counter++;
(gdb) 
0x00000144	70		cpu_irq_critical_section_counter++;
(gdb) 
71	}
(gdb) 
system_gclk_chan_get_hz (channel=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:459
459		gen_id = GCLK->PCHCTRL[channel].bit.GEN;
(gdb) 
0x00000ef6	459		gen_id = GCLK->PCHCTRL[channel].bit.GEN;
(gdb) 
0x00000ef8	459		gen_id = GCLK->PCHCTRL[channel].bit.GEN;
(gdb) 
0x00000efa	459		gen_id = GCLK->PCHCTRL[channel].bit.GEN;
(gdb) 
0x00000efc	459		gen_id = GCLK->PCHCTRL[channel].bit.GEN;
(gdb) 
0x00000efe	459		gen_id = GCLK->PCHCTRL[channel].bit.GEN;
(gdb) 
system_interrupt_leave_critical_section ()
    at ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:182
182		cpu_irq_leave_critical();
(gdb) 
0x00000f02	182		cpu_irq_leave_critical();
(gdb) 
cpu_irq_leave_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:78
78		cpu_irq_critical_section_counter--;
(gdb) 
0x00000156	78		cpu_irq_critical_section_counter--;
(gdb) 
0x00000158	78		cpu_irq_critical_section_counter--;
(gdb) 
0x0000015a	78		cpu_irq_critical_section_counter--;
(gdb) 
82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x0000015e	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000160	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000162	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000164	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000166	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000168	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
83			cpu_irq_enable();
(gdb) 
0x0000016c	83			cpu_irq_enable();
(gdb) 
0x0000016e	83			cpu_irq_enable();
(gdb) 
__DMB () at ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h:357
357	  __ASM volatile ("dmb");
(gdb) 
__enable_irq () at ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h:320
320	  __ASM volatile ("cpsie i");
(gdb) 
cpu_irq_leave_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:85
85	}
(gdb) 
system_gclk_chan_get_hz (channel=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:463
463		return system_gclk_gen_get_hz(gen_id);
(gdb) 
0x00000f06	463		return system_gclk_gen_get_hz(gen_id);
(gdb) 
0x00000f08	463		return system_gclk_gen_get_hz(gen_id);
(gdb) 
system_gclk_gen_get_hz (generator=0 '00') at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:276
276	{
(gdb) 
0x00000df6	276	{
(gdb) 
system_gclk_is_syncing (generator=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:70
70		 if (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 <SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 <SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 <SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 <SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 <SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 << generator )){
(gdb) 
system_gclk_gen_get_hz (generator=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:277
277		while (system_gclk_is_syncing(generator)) {
(gdb) 
0x00000e06	277		while (system_gclk_is_syncing(generator)) {
(gdb) 
system_interrupt_enter_critical_section ()
    at ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:169
169		cpu_irq_enter_critical();
(gdb) 
0x00000e0a	169		cpu_irq_enter_critical();
(gdb) 
cpu_irq_enter_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:59
59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
0x00000116	59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
0x00000118	59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
0x0000011a	59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
__get_PRIMASK () at ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h:471
471	  __ASM volatile ("MRS %0, primask" : "=r" (result) );
(gdb) 
cpu_irq_enter_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:60
60			if (cpu_irq_is_enabled()) {
(gdb) 
0x00000122	60			if (cpu_irq_is_enabled()) {
(gdb) 
__disable_irq () at ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h:331
331	  __ASM volatile ("cpsid i");
(gdb) 
__DMB () at ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h:357
357	  __ASM volatile ("dmb");
(gdb) 
cpu_irq_enter_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:61
61				cpu_irq_disable();
(gdb) 
0x0000012c	61				cpu_irq_disable();
(gdb) 
0x0000012e	61				cpu_irq_disable();
(gdb) 
62				cpu_irq_prev_interrupt_state = true;
(gdb) 
0x00000132	62				cpu_irq_prev_interrupt_state = true;
(gdb) 
0x00000134	62				cpu_irq_prev_interrupt_state = true;
(gdb) 
0x00000136	62				cpu_irq_prev_interrupt_state = true;
(gdb) 
70		cpu_irq_critical_section_counter++;
(gdb) 
0x00000140	70		cpu_irq_critical_section_counter++;
(gdb) 
0x00000142	70		cpu_irq_critical_section_counter++;
(gdb) 
0x00000144	70		cpu_irq_critical_section_counter++;
(gdb) 
71	}
(gdb) 
system_gclk_gen_get_hz (generator=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:285
285				(enum system_clock_source)GCLK->GENCTRL[generator].bit.SRC);
(gdb) 
0x00000e0e	285				(enum system_clock_source)GCLK->GENCTRL[generator].bit.SRC);
(gdb) 
0x00000e10	285				(enum system_clock_source)GCLK->GENCTRL[generator].bit.SRC);
(gdb) 
0x00000e12	285				(enum system_clock_source)GCLK->GENCTRL[generator].bit.SRC);
(gdb) 
0x00000e14	285				(enum system_clock_source)GCLK->GENCTRL[generator].bit.SRC);
(gdb) 
0x00000e16	285				(enum system_clock_source)GCLK->GENCTRL[generator].bit.SRC);
(gdb) 
284		uint32_t gen_input_hz = system_clock_source_get_hz(
(gdb) 
0x00000e1a	284		uint32_t gen_input_hz = system_clock_source_get_hz(
(gdb) 
system_clock_source_get_hz (clock_source=SYSTEM_CLOCK_SOURCE_OSC16M)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/clock.c:198
198	{
(gdb) 
199		switch (clock_source) {
(gdb) 
0x00000b14	199		switch (clock_source) {
(gdb) 
0x00000b16	199		switch (clock_source) {
(gdb) 
0x00000b18	199		switch (clock_source) {
(gdb) 
0x00000b1a	199		switch (clock_source) {
(gdb) 
0x00000b1c	199		switch (clock_source) {
(gdb) 
204			return (OSCCTRL->OSC16MCTRL.bit.FSEL+1)*4000000UL;
(gdb) 
0x00000b2c	204			return (OSCCTRL->OSC16MCTRL.bit.FSEL+1)*4000000UL;
(gdb) 
0x00000b2e	204			return (OSCCTRL->OSC16MCTRL.bit.FSEL+1)*4000000UL;
(gdb) 
0x00000b30	204			return (OSCCTRL->OSC16MCTRL.bit.FSEL+1)*4000000UL;
(gdb) 
0x00000b32	204			return (OSCCTRL->OSC16MCTRL.bit.FSEL+1)*4000000UL;
(gdb) 
0x00000b34	204			return (OSCCTRL->OSC16MCTRL.bit.FSEL+1)*4000000UL;
(gdb) 
0x00000b36	204			return (OSCCTRL->OSC16MCTRL.bit.FSEL+1)*4000000UL;
(gdb) 
0x00000b38	204			return (OSCCTRL->OSC16MCTRL.bit.FSEL+1)*4000000UL;
(gdb) 
242	}
(gdb) 
0x00000e1c in system_gclk_gen_get_hz (generator=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:284
284		uint32_t gen_input_hz = system_clock_source_get_hz(
(gdb) 
287		uint8_t divsel = GCLK->GENCTRL[generator].bit.DIVSEL;
(gdb) 
0x00000e20	287		uint8_t divsel = GCLK->GENCTRL[generator].bit.DIVSEL;
(gdb) 
0x00000e22	287		uint8_t divsel = GCLK->GENCTRL[generator].bit.DIVSEL;
(gdb) 
288		uint32_t divider = GCLK->GENCTRL[generator].bit.DIV;
(gdb) 
0x00000e26	288		uint32_t divider = GCLK->GENCTRL[generator].bit.DIV;
(gdb) 
system_interrupt_leave_critical_section ()
    at ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:182
182		cpu_irq_leave_critical();
(gdb) 
0x00000e2a	182		cpu_irq_leave_critical();
(gdb) 
cpu_irq_leave_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:78
78		cpu_irq_critical_section_counter--;
(gdb) 
0x00000156	78		cpu_irq_critical_section_counter--;
(gdb) 
0x00000158	78		cpu_irq_critical_section_counter--;
(gdb) 
0x0000015a	78		cpu_irq_critical_section_counter--;
(gdb) 
82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x0000015e	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000160	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000162	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000164	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000166	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000168	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
83			cpu_irq_enable();
(gdb) 
0x0000016c	83			cpu_irq_enable();
(gdb) 
0x0000016e	83			cpu_irq_enable();
(gdb) 
__DMB () at ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h:357
357	  __ASM volatile ("dmb");
(gdb) 
__enable_irq () at ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h:320
320	  __ASM volatile ("cpsie i");
(gdb) 
cpu_irq_leave_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:85
85	}
(gdb) 
system_gclk_gen_get_hz (generator=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:293
293		if (!divsel && divider > 1) {
(gdb) 
0x00000e2e	293		if (!divsel && divider > 1) {
(gdb) 
0x00000e30	293		if (!divsel && divider > 1) {
(gdb) 
0x00000e32	293		if (!divsel && divider > 1) {
(gdb) 
300	}
(gdb) 
0x00000e46	300	}
(gdb) 
system_gclk_chan_get_hz (channel=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:464
464	}
(gdb) 
0x00000338 in _i2c_master_set_config (config=0x20002068, module=0x2000008c )
    at ../src/ASF/sam0/drivers/sercom/i2c/i2c_samd21_r21_d10_d11_l21/i2c_master.c:175
175		tmp_baud = (int32_t)(div_ceil(
(gdb) 
0x0000033a	175		tmp_baud = (int32_t)(div_ceil(
(gdb) 
0x0000033c	175		tmp_baud = (int32_t)(div_ceil(
(gdb) 
0x0000033e	175		tmp_baud = (int32_t)(div_ceil(
(gdb) 
0x00000340	175		tmp_baud = (int32_t)(div_ceil(
(gdb) 
0x00000342	175		tmp_baud = (int32_t)(div_ceil(
(gdb) 
0x00000344	175		tmp_baud = (int32_t)(div_ceil(
(gdb) 
0x00000346	175		tmp_baud = (int32_t)(div_ceil(
(gdb) 
0x000011d0 in __udivsi3 ()
(gdb) 
0x000011d2 in __udivsi3 ()
(gdb) 
0x000011d4 in __udivsi3 ()
(gdb) 
0x000011d6 in __udivsi3 ()
(gdb) 
0x000011d8 in __udivsi3 ()
(gdb) 
0x000011da in __udivsi3 ()
(gdb) 
0x000011dc in __udivsi3 ()
(gdb) 
0x000011de in __udivsi3 ()
(gdb) 
0x000011e0 in __udivsi3 ()
(gdb) 
0x000011e2 in __udivsi3 ()
(gdb) 
0x000011e4 in __udivsi3 ()
(gdb) 
0x000011e6 in __udivsi3 ()
(gdb) 
0x000011e8 in __udivsi3 ()
(gdb) 
0x000011ea in __udivsi3 ()
(gdb) 
0x000011ec in __udivsi3 ()
(gdb) 
0x000011ee in __udivsi3 ()
(gdb) 
0x000011e2 in __udivsi3 ()
(gdb) 
0x000011e4 in __udivsi3 ()
(gdb) 
0x000011e6 in __udivsi3 ()
(gdb) 
0x000011e8 in __udivsi3 ()
(gdb) 
0x000011ea in __udivsi3 ()
(gdb) 
0x000011ec in __udivsi3 ()
(gdb) 
0x000011ee in __udivsi3 ()
(gdb) 
0x000011e2 in __udivsi3 ()
(gdb) 
0x000011e4 in __udivsi3 ()
(gdb) 
0x000011e6 in __udivsi3 ()
(gdb) 
0x000011e8 in __udivsi3 ()
(gdb) 
0x000011f0 in __udivsi3 ()
(gdb) 
0x000011f2 in __udivsi3 ()
(gdb) 
0x000011f4 in __udivsi3 ()
(gdb) 
0x000011f6 in __udivsi3 ()
(gdb) 
0x000011f8 in __udivsi3 ()
(gdb) 
0x00001200 in __udivsi3 ()
(gdb) 
0x00001202 in __udivsi3 ()
(gdb) 
0x00001208 in __udivsi3 ()
(gdb) 
0x0000120a in __udivsi3 ()
(gdb) 
0x0000120c in __udivsi3 ()
(gdb) 
0x00001214 in __udivsi3 ()
(gdb) 
0x00001216 in __udivsi3 ()
(gdb) 
0x00001218 in __udivsi3 ()
(gdb) 
0x00001220 in __udivsi3 ()
(gdb) 
0x00001222 in __udivsi3 ()
(gdb) 
0x00001224 in __udivsi3 ()
(gdb) 
0x0000122c in __udivsi3 ()
(gdb) 
0x0000122e in __udivsi3 ()
(gdb) 
0x00001230 in __udivsi3 ()
(gdb) 
0x00001232 in __udivsi3 ()
(gdb) 
0x00001234 in __udivsi3 ()
(gdb) 
0x00001236 in __udivsi3 ()
(gdb) 
0x00001200 in __udivsi3 ()
(gdb) 
0x00001202 in __udivsi3 ()
(gdb) 
0x00001204 in __udivsi3 ()
(gdb) 
0x00001206 in __udivsi3 ()
(gdb) 
0x00001208 in __udivsi3 ()
(gdb) 
0x0000120a in __udivsi3 ()
(gdb) 
0x0000120c in __udivsi3 ()
(gdb) 
0x00001214 in __udivsi3 ()
(gdb) 
0x00001216 in __udivsi3 ()
(gdb) 
0x00001218 in __udivsi3 ()
(gdb) 
0x0000121a in __udivsi3 ()
(gdb) 
0x0000121c in __udivsi3 ()
(gdb) 
0x0000121e in __udivsi3 ()
(gdb) 
0x00001220 in __udivsi3 ()
(gdb) 
0x00001222 in __udivsi3 ()
(gdb) 
0x00001224 in __udivsi3 ()
(gdb) 
0x0000122c in __udivsi3 ()
(gdb) 
0x0000122e in __udivsi3 ()
(gdb) 
0x00001230 in __udivsi3 ()
(gdb) 
0x00001232 in __udivsi3 ()
(gdb) 
0x00001234 in __udivsi3 ()
(gdb) 
0x00001236 in __udivsi3 ()
(gdb) 
0x00001200 in __udivsi3 ()
(gdb) 
0x00001202 in __udivsi3 ()
(gdb) 
0x00001208 in __udivsi3 ()
(gdb) 
0x0000120a in __udivsi3 ()
(gdb) 
0x0000120c in __udivsi3 ()
(gdb) 
0x0000120e in __udivsi3 ()
(gdb) 
0x00001210 in __udivsi3 ()
(gdb) 
0x00001212 in __udivsi3 ()
(gdb) 
0x00001214 in __udivsi3 ()
(gdb) 
0x00001216 in __udivsi3 ()
(gdb) 
0x00001218 in __udivsi3 ()
(gdb) 
0x0000121a in __udivsi3 ()
(gdb) 
0x0000121c in __udivsi3 ()
(gdb) 
0x0000121e in __udivsi3 ()
(gdb) 
0x00001220 in __udivsi3 ()
(gdb) 
0x00001222 in __udivsi3 ()
(gdb) 
0x00001224 in __udivsi3 ()
(gdb) 
0x00001226 in __udivsi3 ()
(gdb) 
0x00001228 in __udivsi3 ()
(gdb) 
0x0000122a in __udivsi3 ()
(gdb) 
0x0000122c in __udivsi3 ()
(gdb) 
0x0000122e in __udivsi3 ()
(gdb) 
0x00001230 in __udivsi3 ()
(gdb) 
0x00001232 in __udivsi3 ()
(gdb) 
0x00001238 in __udivsi3 ()
(gdb) 
0x0000123a in __udivsi3 ()
(gdb) 
0x0000123c in __udivsi3 ()
(gdb) 
_i2c_master_set_config (config=0x20002068, module=0x2000008c )
    at ../src/ASF/sam0/drivers/sercom/i2c/i2c_samd21_r21_d10_d11_l21/i2c_master.c:177
177					(2000*(config->baud_rate))) - 5);
(gdb) 
180		if (tmp_baud > 255 || tmp_baud  255 || tmp_baud < 0) {
(gdb) 
185			tmp_baud_hs = (int32_t)(div_ceil(
(gdb) 
0x00000350	185			tmp_baud_hs = (int32_t)(div_ceil(
(gdb) 
0x00000352	185			tmp_baud_hs = (int32_t)(div_ceil(
(gdb) 
system_gclk_chan_get_hz (channel=20 '24') at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:454
454	{
(gdb) 
0x00000eee	454	{
(gdb) 
system_interrupt_enter_critical_section ()
    at ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:169
169		cpu_irq_enter_critical();
(gdb) 
0x00000ef2	169		cpu_irq_enter_critical();
(gdb) 
cpu_irq_enter_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:59
59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
0x00000116	59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
0x00000118	59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
0x0000011a	59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
__get_PRIMASK () at ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h:471
471	  __ASM volatile ("MRS %0, primask" : "=r" (result) );
(gdb) 
cpu_irq_enter_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:60
60			if (cpu_irq_is_enabled()) {
(gdb) 
0x00000122	60			if (cpu_irq_is_enabled()) {
(gdb) 
__disable_irq () at ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h:331
331	  __ASM volatile ("cpsid i");
(gdb) 
__DMB () at ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h:357
357	  __ASM volatile ("dmb");
(gdb) 
cpu_irq_enter_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:61
61				cpu_irq_disable();
(gdb) 
0x0000012c	61				cpu_irq_disable();
(gdb) 
0x0000012e	61				cpu_irq_disable();
(gdb) 
62				cpu_irq_prev_interrupt_state = true;
(gdb) 
0x00000132	62				cpu_irq_prev_interrupt_state = true;
(gdb) 
0x00000134	62				cpu_irq_prev_interrupt_state = true;
(gdb) 
0x00000136	62				cpu_irq_prev_interrupt_state = true;
(gdb) 
70		cpu_irq_critical_section_counter++;
(gdb) 
0x00000140	70		cpu_irq_critical_section_counter++;
(gdb) 
0x00000142	70		cpu_irq_critical_section_counter++;
(gdb) 
0x00000144	70		cpu_irq_critical_section_counter++;
(gdb) 
71	}
(gdb) 
system_gclk_chan_get_hz (channel=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:459
459		gen_id = GCLK->PCHCTRL[channel].bit.GEN;
(gdb) 
0x00000ef6	459		gen_id = GCLK->PCHCTRL[channel].bit.GEN;
(gdb) 
0x00000ef8	459		gen_id = GCLK->PCHCTRL[channel].bit.GEN;
(gdb) 
0x00000efa	459		gen_id = GCLK->PCHCTRL[channel].bit.GEN;
(gdb) 
0x00000efc	459		gen_id = GCLK->PCHCTRL[channel].bit.GEN;
(gdb) 
0x00000efe	459		gen_id = GCLK->PCHCTRL[channel].bit.GEN;
(gdb) 
system_interrupt_leave_critical_section ()
    at ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:182
182		cpu_irq_leave_critical();
(gdb) 
0x00000f02	182		cpu_irq_leave_critical();
(gdb) 
cpu_irq_leave_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:78
78		cpu_irq_critical_section_counter--;
(gdb) 
0x00000156	78		cpu_irq_critical_section_counter--;
(gdb) 
0x00000158	78		cpu_irq_critical_section_counter--;
(gdb) 
0x0000015a	78		cpu_irq_critical_section_counter--;
(gdb) 
82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x0000015e	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000160	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000162	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000164	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000166	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000168	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
83			cpu_irq_enable();
(gdb) 
0x0000016c	83			cpu_irq_enable();
(gdb) 
0x0000016e	83			cpu_irq_enable();
(gdb) 
__DMB () at ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h:357
357	  __ASM volatile ("dmb");
(gdb) 
__enable_irq () at ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h:320
320	  __ASM volatile ("cpsie i");
(gdb) 
cpu_irq_leave_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:85
85	}
(gdb) 
system_gclk_chan_get_hz (channel=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:463
463		return system_gclk_gen_get_hz(gen_id);
(gdb) 
0x00000f06	463		return system_gclk_gen_get_hz(gen_id);
(gdb) 
0x00000f08	463		return system_gclk_gen_get_hz(gen_id);
(gdb) 
system_gclk_gen_get_hz (generator=0 '00') at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:276
276	{
(gdb) 
0x00000df6	276	{
(gdb) 
system_gclk_is_syncing (generator=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:70
70		 if (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 <SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 <SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 <SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 <SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 <SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 << generator )){
(gdb) 
system_gclk_gen_get_hz (generator=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:277
277		while (system_gclk_is_syncing(generator)) {
(gdb) 
0x00000e06	277		while (system_gclk_is_syncing(generator)) {
(gdb) 
system_interrupt_enter_critical_section ()
    at ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:169
169		cpu_irq_enter_critical();
(gdb) 
0x00000e0a	169		cpu_irq_enter_critical();
(gdb) 
cpu_irq_enter_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:59
59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
0x00000116	59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
0x00000118	59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
0x0000011a	59		if (cpu_irq_critical_section_counter == 0) {
(gdb) 
__get_PRIMASK () at ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h:471
471	  __ASM volatile ("MRS %0, primask" : "=r" (result) );
(gdb) 
cpu_irq_enter_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:60
60			if (cpu_irq_is_enabled()) {
(gdb) 
0x00000122	60			if (cpu_irq_is_enabled()) {
(gdb) 
__disable_irq () at ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h:331
331	  __ASM volatile ("cpsid i");
(gdb) 
__DMB () at ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h:357
357	  __ASM volatile ("dmb");
(gdb) 
cpu_irq_enter_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:61
61				cpu_irq_disable();
(gdb) 
0x0000012c	61				cpu_irq_disable();
(gdb) 
0x0000012e	61				cpu_irq_disable();
(gdb) 
62				cpu_irq_prev_interrupt_state = true;
(gdb) 
0x00000132	62				cpu_irq_prev_interrupt_state = true;
(gdb) 
0x00000134	62				cpu_irq_prev_interrupt_state = true;
(gdb) 
0x00000136	62				cpu_irq_prev_interrupt_state = true;
(gdb) 
70		cpu_irq_critical_section_counter++;
(gdb) 
0x00000140	70		cpu_irq_critical_section_counter++;
(gdb) 
0x00000142	70		cpu_irq_critical_section_counter++;
(gdb) 
0x00000144	70		cpu_irq_critical_section_counter++;
(gdb) 
71	}
(gdb) 
system_gclk_gen_get_hz (generator=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:285
285				(enum system_clock_source)GCLK->GENCTRL[generator].bit.SRC);
(gdb) 
0x00000e0e	285				(enum system_clock_source)GCLK->GENCTRL[generator].bit.SRC);
(gdb) 
0x00000e10	285				(enum system_clock_source)GCLK->GENCTRL[generator].bit.SRC);
(gdb) 
0x00000e12	285				(enum system_clock_source)GCLK->GENCTRL[generator].bit.SRC);
(gdb) 
0x00000e14	285				(enum system_clock_source)GCLK->GENCTRL[generator].bit.SRC);
(gdb) 
0x00000e16	285				(enum system_clock_source)GCLK->GENCTRL[generator].bit.SRC);
(gdb) 
284		uint32_t gen_input_hz = system_clock_source_get_hz(
(gdb) 
0x00000e1a	284		uint32_t gen_input_hz = system_clock_source_get_hz(
(gdb) 
system_clock_source_get_hz (clock_source=SYSTEM_CLOCK_SOURCE_OSC16M)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/clock.c:198
198	{
(gdb) 
199		switch (clock_source) {
(gdb) 
0x00000b14	199		switch (clock_source) {
(gdb) 
0x00000b16	199		switch (clock_source) {
(gdb) 
0x00000b18	199		switch (clock_source) {
(gdb) 
0x00000b1a	199		switch (clock_source) {
(gdb) 
0x00000b1c	199		switch (clock_source) {
(gdb) 
204			return (OSCCTRL->OSC16MCTRL.bit.FSEL+1)*4000000UL;
(gdb) 
0x00000b2c	204			return (OSCCTRL->OSC16MCTRL.bit.FSEL+1)*4000000UL;
(gdb) 
0x00000b2e	204			return (OSCCTRL->OSC16MCTRL.bit.FSEL+1)*4000000UL;
(gdb) 
0x00000b30	204			return (OSCCTRL->OSC16MCTRL.bit.FSEL+1)*4000000UL;
(gdb) 
0x00000b32	204			return (OSCCTRL->OSC16MCTRL.bit.FSEL+1)*4000000UL;
(gdb) 
0x00000b34	204			return (OSCCTRL->OSC16MCTRL.bit.FSEL+1)*4000000UL;
(gdb) 
0x00000b36	204			return (OSCCTRL->OSC16MCTRL.bit.FSEL+1)*4000000UL;
(gdb) 
0x00000b38	204			return (OSCCTRL->OSC16MCTRL.bit.FSEL+1)*4000000UL;
(gdb) 
242	}
(gdb) 
0x00000e1c in system_gclk_gen_get_hz (generator=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:284
284		uint32_t gen_input_hz = system_clock_source_get_hz(
(gdb) 
287		uint8_t divsel = GCLK->GENCTRL[generator].bit.DIVSEL;
(gdb) 
0x00000e20	287		uint8_t divsel = GCLK->GENCTRL[generator].bit.DIVSEL;
(gdb) 
0x00000e22	287		uint8_t divsel = GCLK->GENCTRL[generator].bit.DIVSEL;
(gdb) 
288		uint32_t divider = GCLK->GENCTRL[generator].bit.DIV;
(gdb) 
0x00000e26	288		uint32_t divider = GCLK->GENCTRL[generator].bit.DIV;
(gdb) 
system_interrupt_leave_critical_section ()
    at ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:182
182		cpu_irq_leave_critical();
(gdb) 
0x00000e2a	182		cpu_irq_leave_critical();
(gdb) 
cpu_irq_leave_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:78
78		cpu_irq_critical_section_counter--;
(gdb) 
0x00000156	78		cpu_irq_critical_section_counter--;
(gdb) 
0x00000158	78		cpu_irq_critical_section_counter--;
(gdb) 
0x0000015a	78		cpu_irq_critical_section_counter--;
(gdb) 
82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x0000015e	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000160	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000162	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000164	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000166	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
0x00000168	82		if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
(gdb) 
83			cpu_irq_enable();
(gdb) 
0x0000016c	83			cpu_irq_enable();
(gdb) 
0x0000016e	83			cpu_irq_enable();
(gdb) 
__DMB () at ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h:357
357	  __ASM volatile ("dmb");
(gdb) 
__enable_irq () at ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h:320
320	  __ASM volatile ("cpsie i");
(gdb) 
cpu_irq_leave_critical () at ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c:85
85	}
(gdb) 
system_gclk_gen_get_hz (generator=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:293
293		if (!divsel && divider > 1) {
(gdb) 
0x00000e2e	293		if (!divsel && divider > 1) {
(gdb) 
0x00000e30	293		if (!divsel && divider > 1) {
(gdb) 
0x00000e32	293		if (!divsel && divider > 1) {
(gdb) 
300	}
(gdb) 
0x00000e46	300	}
(gdb) 
system_gclk_chan_get_hz (channel=)
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:464
464	}
(gdb) 
0x00000354 in _i2c_master_set_config (config=0x20002068, module=)
    at ../src/ASF/sam0/drivers/sercom/i2c/i2c_samd21_r21_d10_d11_l21/i2c_master.c:185
185			tmp_baud_hs = (int32_t)(div_ceil(
(gdb) 
0x00000356	185			tmp_baud_hs = (int32_t)(div_ceil(
(gdb) 
0x00000358	185			tmp_baud_hs = (int32_t)(div_ceil(
(gdb) 
0x0000035a	185			tmp_baud_hs = (int32_t)(div_ceil(
(gdb) 
0x0000035c	185			tmp_baud_hs = (int32_t)(div_ceil(
(gdb) 
0x0000035e	185			tmp_baud_hs = (int32_t)(div_ceil(
(gdb) 
0x00000360	185			tmp_baud_hs = (int32_t)(div_ceil(
(gdb) 
0x00000362	185			tmp_baud_hs = (int32_t)(div_ceil(
(gdb) 
0x000011d0 in __udivsi3 ()
(gdb) 
0x000011d2 in __udivsi3 ()
(gdb) 
0x000011d4 in __udivsi3 ()
(gdb) 
0x000011d6 in __udivsi3 ()
(gdb) 
0x000011d8 in __udivsi3 ()
(gdb) 
0x000011da in __udivsi3 ()
(gdb) 
0x000011dc in __udivsi3 ()
(gdb) 
0x000011de in __udivsi3 ()
(gdb) 
0x000011e0 in __udivsi3 ()
(gdb) 
0x000011e2 in __udivsi3 ()
(gdb) 
0x000011e4 in __udivsi3 ()
(gdb) 
0x000011e6 in __udivsi3 ()
(gdb) 
0x000011e8 in __udivsi3 ()
(gdb) 
0x000011ea in __udivsi3 ()
(gdb) 
0x000011ec in __udivsi3 ()
(gdb) 
0x000011ee in __udivsi3 ()
(gdb) 
0x000011e2 in __udivsi3 ()
(gdb) 
0x000011e4 in __udivsi3 ()
(gdb) 
0x000011e6 in __udivsi3 ()
(gdb) 
0x000011e8 in __udivsi3 ()
(gdb) 
0x000011f0 in __udivsi3 ()
(gdb) 
0x000011f2 in __udivsi3 ()
(gdb) 
0x000011f4 in __udivsi3 ()
(gdb) 
0x000011f6 in __udivsi3 ()
(gdb) 
0x000011f8 in __udivsi3 ()
(gdb) 
0x00001200 in __udivsi3 ()
(gdb) 
0x00001202 in __udivsi3 ()
(gdb) 
0x00001208 in __udivsi3 ()
(gdb) 
0x0000120a in __udivsi3 ()
(gdb) 
0x0000120c in __udivsi3 ()
(gdb) 
0x00001214 in __udivsi3 ()
(gdb) 
0x00001216 in __udivsi3 ()
(gdb) 
0x00001218 in __udivsi3 ()
(gdb) 
0x00001220 in __udivsi3 ()
(gdb) 
0x00001222 in __udivsi3 ()
(gdb) 
0x00001224 in __udivsi3 ()
(gdb) 
0x0000122c in __udivsi3 ()
(gdb) 
0x0000122e in __udivsi3 ()
(gdb) 
0x00001230 in __udivsi3 ()
(gdb) 
0x00001232 in __udivsi3 ()
(gdb) 
0x00001234 in __udivsi3 ()
(gdb) 
0x00001236 in __udivsi3 ()
(gdb) 
0x00001200 in __udivsi3 ()
(gdb) 
0x00001202 in __udivsi3 ()
(gdb) 
0x00001204 in __udivsi3 ()
(gdb) 
0x00001206 in __udivsi3 ()
(gdb) 
0x00001208 in __udivsi3 ()
(gdb) 
0x0000120a in __udivsi3 ()
(gdb) 
0x0000120c in __udivsi3 ()
(gdb) 
0x0000120e in __udivsi3 ()
(gdb) 
0x00001210 in __udivsi3 ()
(gdb) 
0x00001212 in __udivsi3 ()
(gdb) 
0x00001214 in __udivsi3 ()
(gdb) 
0x00001216 in __udivsi3 ()
(gdb) 
0x00001218 in __udivsi3 ()
(gdb) 
0x00001220 in __udivsi3 ()
(gdb) 
0x00001222 in __udivsi3 ()
(gdb) 
0x00001224 in __udivsi3 ()
(gdb) 
0x0000122c in __udivsi3 ()
(gdb) 
0x0000122e in __udivsi3 ()
(gdb) 
0x00001230 in __udivsi3 ()
(gdb) 
0x00001232 in __udivsi3 ()
(gdb) 
0x00001238 in __udivsi3 ()
(gdb) 
0x0000123a in __udivsi3 ()
(gdb) 
0x0000123c in __udivsi3 ()
(gdb) 
_i2c_master_set_config (config=0x20002068, module=)
    at ../src/ASF/sam0/drivers/sercom/i2c/i2c_samd21_r21_d10_d11_l21/i2c_master.c:187
187					(2000*(config->baud_rate_high_speed))) - 1);
(gdb) 
190			if (tmp_baud_hs > 255 || tmp_baud_hs  255 || tmp_baud_hs BAUD.reg = SERCOM_I2CM_BAUD_BAUD(tmp_baud) |
(gdb) 
0x00000378	197			i2c_module->BAUD.reg = SERCOM_I2CM_BAUD_BAUD(tmp_baud) |
(gdb) 
0x0000037a	197			i2c_module->BAUD.reg = SERCOM_I2CM_BAUD_BAUD(tmp_baud) |
(gdb) 
0x0000037c	197			i2c_module->BAUD.reg = SERCOM_I2CM_BAUD_BAUD(tmp_baud) |
(gdb) 
92		enum status_code tmp_status_code = STATUS_OK;
(gdb) 
i2c_master_init (module=, hw=, config=0x20002068)
    at ../src/ASF/sam0/drivers/sercom/i2c/i2c_samd21_r21_d10_d11_l21/i2c_master.c:291
291	}
(gdb) 
0x00000382 in i2c_master_init (module=, hw=, config=)
    at ../src/ASF/sam0/drivers/sercom/i2c/i2c_samd21_r21_d10_d11_l21/i2c_master.c:291
291	}
(gdb) 
Cannot access memory at address 0x123b4246
0x00000384 in i2c_master_init (module=, hw=, config=)
    at ../src/ASF/sam0/drivers/sercom/i2c/i2c_samd21_r21_d10_d11_l21/i2c_master.c:291
291	}
(gdb) 
0x00000386	291	}
(gdb) 
0x000010f0 in configure_i2c () at ../src/qs_i2c_master_callback.c:104
104		while(i2c_master_init(&i2c_master_instance, SERCOM2, &config_i2c_master)     \
(gdb) 
0x000010f2	104		while(i2c_master_init(&i2c_master_instance, SERCOM2, &config_i2c_master)     \
(gdb) 
i2c_master_enable (module=0x2000008c )
    at ../src/ASF/sam0/drivers/sercom/i2c/i2c_master.h:482
482		SercomI2cm *const i2c_module = &(module->hw->I2CM);
(gdb) 
0x000010f6	482		SercomI2cm *const i2c_module = &(module->hw->I2CM);
(gdb) 
i2c_master_is_syncing (module=0x2000008c )
    at ../src/ASF/sam0/drivers/sercom/i2c/i2c_master.h:384
384		return (i2c_hw->SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_MASK);
(gdb) 
0x000010fa	384		return (i2c_hw->SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_MASK);
(gdb) 
_i2c_master_wait_for_sync (module=0x2000008c )
    at ../src/ASF/sam0/drivers/sercom/i2c/i2c_master.h:403
403		while (i2c_master_is_syncing(module)) {
(gdb) 
0x000010fe	403		while (i2c_master_is_syncing(module)) {
(gdb) 
i2c_master_enable (module=0x2000008c )
    at ../src/ASF/sam0/drivers/sercom/i2c/i2c_master.h:491
491		i2c_module->CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE;
(gdb) 
0x00001102	491		i2c_module->CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE;
(gdb) 
0x00001104	491		i2c_module->CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE;
(gdb) 
0x00001106	491		i2c_module->CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE;
(gdb) 
495		system_interrupt_enable(_sercom_get_interrupt_vector(module->hw));
(gdb) 
0x0000110a	495		system_interrupt_enable(_sercom_get_interrupt_vector(module->hw));
(gdb) 
0x0000110c	495		system_interrupt_enable(_sercom_get_interrupt_vector(module->hw));
(gdb) 
0x0000110e	495		system_interrupt_enable(_sercom_get_interrupt_vector(module->hw));
(gdb) 
_sercom_get_interrupt_vector (sercom_instance=0x42000800)
    at ../src/ASF/sam0/drivers/sercom/sercom_interrupt.c:127
127	{
(gdb) 
0x00000a86	127	{
(gdb) 
0x00000a88	127	{
(gdb) 
128		const uint8_t sercom_int_vectors[SERCOM_INST_NUM] =
(gdb) 
0x00000a8c	128		const uint8_t sercom_int_vectors[SERCOM_INST_NUM] =
(gdb) 
0x00000a8e	128		const uint8_t sercom_int_vectors[SERCOM_INST_NUM] =
(gdb) 
0x00000a90	128		const uint8_t sercom_int_vectors[SERCOM_INST_NUM] =
(gdb) 
0x00000a92	128		const uint8_t sercom_int_vectors[SERCOM_INST_NUM] =
(gdb) 
0x000012bc in memcpy ()
(gdb) 
0x000012be in memcpy ()
(gdb) 
0x000012c0 in memcpy ()
(gdb) 
0x000012c2 in memcpy ()
(gdb) 
0x000012c4 in memcpy ()
(gdb) 
0x000012c6 in memcpy ()
(gdb) 
0x000012c8 in memcpy ()
(gdb) 
0x000012ca in memcpy ()
(gdb) 
0x000012c0 in memcpy ()
(gdb) 
0x000012c2 in memcpy ()
(gdb) 
0x000012c4 in memcpy ()
(gdb) 
0x000012c6 in memcpy ()
(gdb) 
0x000012c8 in memcpy ()
(gdb) 
0x000012ca in memcpy ()
(gdb) 
0x000012c0 in memcpy ()
(gdb) 
0x000012c2 in memcpy ()
(gdb) 
0x000012c4 in memcpy ()
(gdb) 
0x000012c6 in memcpy ()
(gdb) 
0x000012c8 in memcpy ()
(gdb) 
0x000012ca in memcpy ()
(gdb) 
0x000012c0 in memcpy ()
(gdb) 
0x000012c2 in memcpy ()
(gdb) 
0x000012c4 in memcpy ()
(gdb) 
0x000012c6 in memcpy ()
(gdb) 
0x000012c8 in memcpy ()
(gdb) 
0x000012ca in memcpy ()
(gdb) 
0x000012c0 in memcpy ()
(gdb) 
0x000012c2 in memcpy ()
(gdb) 
0x000012c4 in memcpy ()
(gdb) 
0x000012c6 in memcpy ()
(gdb) 
0x000012c8 in memcpy ()
(gdb) 
0x000012ca in memcpy ()
(gdb) 
0x000012c0 in memcpy ()
(gdb) 
0x000012c2 in memcpy ()
(gdb) 
0x000012c4 in memcpy ()
(gdb) 
0x000012c6 in memcpy ()
(gdb) 
0x000012c8 in memcpy ()
(gdb) 
0x000012ca in memcpy ()
(gdb) 
0x000012c0 in memcpy ()
(gdb) 
0x000012c2 in memcpy ()
(gdb) 
0x000012cc in memcpy ()
(gdb) 
_sercom_get_interrupt_vector (sercom_instance=0x42000800)
    at ../src/ASF/sam0/drivers/sercom/sercom_interrupt.c:134
134		uint8_t instance_index = _sercom_get_sercom_inst_index(sercom_instance);
(gdb) 
0x00000a96	134		uint8_t instance_index = _sercom_get_sercom_inst_index(sercom_instance);
(gdb) 
0x00000a98	134		uint8_t instance_index = _sercom_get_sercom_inst_index(sercom_instance);
(gdb) 
_sercom_get_sercom_inst_index (sercom_instance=0x42000800) at ../src/ASF/sam0/drivers/sercom/sercom.c:282
282	{
(gdb) 
0x00000a0a	282	{
(gdb) 
284		Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
(gdb) 
0x00000a0e	284		Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
(gdb) 
0x00000a10	284		Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
(gdb) 
0x00000a12	284		Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
(gdb) 
0x00000a14	284		Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
(gdb) 
0x00000a16	284		Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
(gdb) 
288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
0x00000a1a	288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
0x00000a1c	288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
287		for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
(gdb) 
0x00000a20	287		for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
(gdb) 
288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
0x00000a24	288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
0x00000a26	288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
0x00000a28	288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
287		for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
(gdb) 
0x00000a34	287		for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
(gdb) 
0x00000a36	287		for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
(gdb) 
0x00000a20	287		for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
(gdb) 
288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
0x00000a24	288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
0x00000a26	288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
0x00000a28	288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
0x00000a2a	288			if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
(gdb) 
289				return i;
(gdb) 
0x00000a30	289				return i;
(gdb) 
296	}
(gdb) 
0x00000a3c in _sercom_get_sercom_inst_index (sercom_instance=)
    at ../src/ASF/sam0/drivers/sercom/sercom.c:296
296	}
(gdb) 
_sercom_get_interrupt_vector (sercom_instance=0x42000800)
    at ../src/ASF/sam0/drivers/sercom/sercom_interrupt.c:137
137		return (enum system_interrupt_vector)sercom_int_vectors[instance_index];
(gdb) 
0x00000a9c	137		return (enum system_interrupt_vector)sercom_int_vectors[instance_index];
(gdb) 
138	}
(gdb) 
0x00000aa0 in _sercom_get_interrupt_vector (sercom_instance=)
    at ../src/ASF/sam0/drivers/sercom/sercom_interrupt.c:138
138	}
(gdb) 
system_interrupt_enable (vector=SYSTEM_INTERRUPT_MODULE_SERCOM2)
    at ../src/ASF/sam0/drivers/system/interrupt/system_interrupt.h:258
258		NVIC->ISER[0] = (uint32_t)(1 <ISER[0] = (uint32_t)(1 <ISER[0] = (uint32_t)(1 <ISER[0] = (uint32_t)(1 <ISER[0] = (uint32_t)(1 <ISER[0] = (uint32_t)(1 <ISER[0] = (uint32_t)(1 << ((uint32_t)vector & 0x0000001f));
(gdb) 
i2c_master_enable (module=0x2000008c )
    at ../src/ASF/sam0/drivers/sercom/i2c/i2c_master.h:500
500			if(timeout_counter >= (module->unknown_bus_state_timeout)) {
(gdb) 
485		uint32_t timeout_counter = 0;
(gdb) 
498		while (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(1))) {
(gdb) 
0x00001124	498		while (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(1))) {
(gdb) 
498		while (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(1))) {
(gdb) 

Sigrok and a “cheap” Saleae clone can save your life (I meant your time)

An affordable, inexpensive and “cheap” Saleae clone could save your day (really).

You could find it for less than U$ 10:
http://www.electrodragon.com/product/saleae-usb-logic-analyzer-24m-8-channel/

I was implementing a NuttX driver for BMP180 over I2C, but was failing to get it working and it was difficult to discover what was going on.

I decided to test my cheap Saleae clone for the first time. The Sigrok tool installation from source code is explained here:

http://marcusjenkins.com/linux/saleae-logic-analyser-clone-with-ubuntu/

Then compared my driver command:

against Adrafruit BMP085/BMP180 commands:

Imediately I noticed I forgot to write the register address that I need to read before issuing the read command.

Just an I2C_WRITE before a I2C_READ fixed the issue!

Related: How to use sigrok to measure real-time signal latency http://blog.savoirfairelinux.com/en/2014/logic-analyzer-visualize-latency-with-sigrok-and-matplotlib/

Update: You need to copy the firmware to Sigrok work:

cp fx2lafw-saleae-logic.fw /usr/local/share/sigrok-firmware/fx2lafw-saleae-logic.fw

I got the firmware from sigrok-firmware-fx2lafw-bin-0.1.3.tar.gz

How to discover what video card and video driver your laptop is using

$ lshw -c video
WARNING: you should run this program as super-user.
*-display UNCLAIMED
description: VGA compatible controller
product: GF108M [GeForce GT 630M]
vendor: NVIDIA Corporation
physical id: 0
bus info: pci@0000:01:00.0
version: a1
width: 64 bits
clock: 33MHz
capabilities: vga_controller bus_master cap_list
configuration: latency=0
resources: memory:f0000000-f0ffffff memory:c0000000-cfffffff memory:d0000000-d1ffffff ioport:3000(size=128) memory:f1000000-f107ffff
*-display
description: VGA compatible controller
product: 3rd Gen Core processor Graphics Controller
vendor: Intel Corporation
physical id: 2
bus info: pci@0000:00:02.0
version: 09
width: 64 bits
clock: 33MHz
capabilities: vga_controller bus_master cap_list rom
configuration: driver=i915 latency=0
resources: irq:44 memory:f1400000-f17fffff memory:e0000000-efffffff ioport:4000(size=64)
WARNING: output may be incomplete or inaccurate, you should run this program as super-user.

$ lsmod | grep i915
i915 784116 3
drm_kms_helper 55071 1 i915
drm 303102 4 i915,drm_kms_helper
i2c_algo_bit 13413 1 i915
video 19476 1 i915

BUT, if your laptop has Nvidia driver, you can check it:

$ ubuntu-drivers devices
== /sys/devices/pci0000:00/0000:00:01.0/0000:01:00.0 ==
modalias : pci:v000010DEd00000DE9sv00001028sd0000055Ebc03sc00i00
vendor : NVIDIA Corporation
model : GF108M [GeForce GT 620M/630M/635M/640M LE]
driver : nvidia-340 – distro non-free
driver : nvidia-driver-390 – distro non-free recommended
driver : xserver-xorg-video-nouveau – distro free builtin

And install the driver:

$ sudo apt install nvidia-driver-390

And install glxinfo tool from mesa-utils package:

$ sudo apt install mesa-utils

Finally you can confirm you are using the NVIDIA driver:

$ glxinfo | grep renderer

OpenGL renderer string: GeForce GT 630M/PCIe/SSE2

Some open-source/open-hardware ODB-II related projects

I was searching for Open-Source/Hardware solutions for OBD-II and found some interesting links:

CANtact:
https://github.com/cantact

Opendiag, An open-source OBD-II to Serial adapter board:

https://jeff.noxon.cc/2013/05/18/opendiag-obd-ii-schematics-pcb-layout/

Opendiag mainling list:
https://groups.yahoo.com/neo/groups/opendiag/info

OBD-II OpenXC firmware:
http://openxcplatform.com/vehicle-interface/firmware.html

PIC based handheld OBDII scanner:
https://code.google.com/p/picobdii/

Hand held OBDII code reader, aka scanner, based on an AVR processor:
https://code.google.com/p/avrobdii/

SDB:ELM327 based ODB2 scan tool for Linux:
https://en.opensuse.org/SDB:ELM327_based_ODB2_scan_tool

ArduinoOBD, A open-source Arduino library for Freematics dongle:
https://github.com/stanleyhuangyc/ArduinoOBD

Sprechen sie Deutsch?
https://www.blafusel.de/obd/obd2_kw_usb-interf.html

More info:
http://www.esatinc.ca/News_Letters/OBD_II_Specifications_and_Connections.pdf

http://www.avt-hq.com/obd_02.pdf

https://github.com/matt2005/AlarmSim/tree/master/collected_samplecode

http://hackaday.com/2013/10/29/can-hacking-protocols/

K-Line (ISO9141 and ISO14230)
https://www.instructables.com/Low-Cost-OBD2-Communications-on-K-line-ISO-9141-2-/

How to compile Python code to native executable

First, you need to create a python application, in this case just a “Hello World” test.py file:

$ cat test.py
print "Hello World"

Convert the Python code in C code using Cython:

$ cython --embed test.py

We need to use “–embed” because we don’t want a shared library, but a real main program.

Compile the generated “test.c” file:

$ gcc test.c -o test `pkg-config --libs --cflags python2`

Test it:

$ ./test 
Hello World

Sources:
http://stackoverflow.com/questions/5105482/compile-main-python-program-using-cython
https://bbs.archlinux.org/viewtopic.php?id=180538
http://www.behnel.de/cython200910/talk.html

Some facts about Atmel SAM L21 microcontroller

The Atmel SAML21 microcontroller has a complex clock structure, in fact even more complex than some high end processors. This complexity brings more flexibility to enable individually each peripheral clock source.

The SAM L21 has nine Clocks Generator, each generator can select a specific clock input (XOSC, GCLK_IN, GCLK_GEN1, OSCULP32K, OSC32K, OSC16M, DFLL48M or DPLL96M). Exception is Generator1 (GCLK_GEN1) that cannot select GCLK_GEN1 (itself) because its clock output can be used as clock input by other Generators.

Each Generator has a internal prescaler to divide the input clock up to 128 (again CLK_GEN1 is exception because it can divide up to 32768). And the Generator output clock can be used by up to 64 Peripheral channels (in the SAML21 there are “only” 35 channels).

Basic Operation

-The GCLK module has 9 Generic Clock Generators

- Up to 64 Peripheral Channels and the Main Clock signal (GCLK_MAIN) can be sourced from Generator

- The clock source selected as input to a Generator can be used directly or prescaled

- The GCLK Module doesn't have a general enable/disable bit

- The GCLK Module can be reset by setting the Software Reset bit (CTRLA.SWRST)

  - All register from GCLK module will be reset, except Per.Channels and associated Generators

- All Generators can be set to run from 1 of 9 clock sources, except GCLK_GEN[1]
  - GCLK_GEN[1] can be used to supply clock for all others 8 Generators

- Each generator GCLK_GEN[x] can be connected to 1 pin (GCLK_IO[y])

- GCLK_GEN[0] is used as GCLK_MAIN

- Each Genarator can be enabled/disabled by setting Generator Enable bit (GENCTRLn.GENEN = 1/0).

- The clock for of each Generator can be selected by setting the Source Select bit (GENCTRL[n].SRC)

  - When changing of clock source the  register SYNCBUSY.GENCTRL_n will remain 1 until the source is fine

- The clock freq of each generator can be divided setting GENCTRLn.DIV
  - If GENCTRLn.DIVSEL = 0 and GENCTRLn.DIV is 0 or 1 the freq. is not divided

- If division factor is odd the Duty cycle will not be 50/50
  - Setting the Improve Duty Cycle (GENCTRLn.IDC) will result in a 50/50 duty cycle

- If Output Enable (GENCTRLn.OE = 1) and GENCTRLn.GENEN = 1 the clock is outputed to GCLK_IO pin

Peripheral Clock

- Before enabling a Peripheral channel the Generator clock needs to be enabled (GENCTRLn.GEN = 1) and
this Generator is already selected as source for the Peripheral Channel (PCHCTRLm.GEN)

- The Peripheral Channel is enabled in the Channel Enable bit (PCHCTRLm.CHEN = 1)

- The Peripheral Channel's Generator (PCHCTRLm.GEN) needs to be set with Channel disabled (PCHCTRLm.CHEN = 0)

- The Peripheral clock configuration can be locked setting Write Lock bit (PCHCTRLm.WRTLOCK=1)

  - When WRTLOCK is set the Generator will be locked, exception is Generator 0 that is sorce of GCLK_MAIN

- In SAM L21 we have 35 Peripheral channels (index 0 up to 34)

GUI for LinuxCNC/Machinekit

There are some nice GUIs for LinuxCNC.

These GUI make LinuxCNC or MachineKit (LinuxCNC fork) control more user friend.

Here I list three more common options:

Axis
This is the original GUI shipped with LinuxCNC LiveCD/Installer distro:
http://linuxcnc.org/docs/html/gui/axis.html

Gmoccapy
Gmoccapy is an alternative to Axis focuses on Touchscreen devices and supports up to 4 axis CNCs:
http://wiki.linuxcnc.org/cgi-bin/wiki.pl?Gmoccapy

QtQuickVcp
QtQuickVcp is the more recent GUI designed to be multi-platform, including Android support:
https://github.com/strahlex/QtQuickVcp

Using Watchpoints in the GDB to verify register access

Watchpoint is a feature similar to Breakpoint, but instead of stopping when the Program Counter reach a function or code line, watchpoint stops when an address memory is read (rwatch), write (watch) or read/write (awatch).

Watchpoints are very useful when you are doing reverse engineering or when you want to debug a code that access many registers.

First we need to know if our processor supports hardware watchpoints:

(gdb) show can-use-hw-watchpoints
Debugger's willingness to use watchpoint hardware is 1.

Case your uP/uC doesn’t, no problem! It will work, but with Software Watchpoint ( *slow* )

Some processors (i.e. PowerPC) support masking a memory position, then any address accessed in this area will generate a stop condition:

(gdb) watch *0xdeadbeef mask 0xffffff00

Unfortunately my microcontroller (ARM Cortex-M0+) doesn’t support:

(gdb) awatch *0x40000000 mask 0xffff0000
This target does not support masked watchpoints.

In this case I need to add many watchpoints manually:

(gdb) b main
Breakpoint 1 at 0x1c3a: file ../src/qs_i2c_master_basic_use.c, line 108.
(gdb) c
Continuing.

Breakpoint 1, main () at ../src/qs_i2c_master_basic_use.c:108
108		system_init();
(gdb) n
113		configure_i2c_master();
(gdb) awatch *0x40000000 mask 0xffff0000
This target does not support masked watchpoints.
(gdb) awatch *0x40002800
Hardware access (read/write) watchpoint 2: *0x40002800
(gdb) awatch *0x40002804
Hardware access (read/write) watchpoint 3: *0x40002804
(gdb) awatch *0x40002808
Hardware access (read/write) watchpoint 4: *0x40002808
(gdb) awatch *0x40002828
Hardware access (read/write) watchpoint 5: *0x40002828
(gdb) awatch *0x400018d0
Hardware access (read/write) watchpoint 6: *0x400018d0
(gdb) awatch *0x42000800
Hardware access (read/write) watchpoint 7: *0x42000800
(gdb) awatch *0x42000804
Hardware access (read/write) watchpoint 8: *0x42000804
(gdb) awatch *0x4200080c
Hardware access (read/write) watchpoint 9: *0x4200080c
(gdb) awatch *0x42000814
Hardware access (read/write) watchpoint 10: *0x42000814
(gdb) awatch *0x42000816
Hardware access (read/write) watchpoint 11: *0x42000816
(gdb) awatch *0x42000818
Hardware access (read/write) watchpoint 12: *0x42000818
(gdb) awatch *0x4200081a
Hardware access (read/write) watchpoint 13: *0x4200081a
(gdb) awatch *0x4200081c
Hardware access (read/write) watchpoint 14: *0x4200081c
(gdb) awatch *0x42000824
Hardware access (read/write) watchpoint 15: *0x42000824
(gdb) awatch *0x42000828
Hardware access (read/write) watchpoint 16: *0x42000828
(gdb) c
Continuing.

Program received signal SIGTRAP, Trace/breakpoint trap.
0x000016f0 in system_gclk_chan_disable (channel=20 '24')
    at ../src/ASF/sam0/drivers/system/clock/clock_saml21/gclk.c:371
371		GCLK->PCHCTRL[channel].reg &= ~GCLK_PCHCTRL_CHEN;

Sources:
http://stackoverflow.com/questions/58851/can-i-set-a-breakpoint-on-memory-access-in-gdb
https://sourceware.org/gdb/onlinedocs/gdb/Set-Watchpoints.html