Probably you already used the two wires SWD interface with some ARM Cortex MCU, but this interface is proprietary, ARM has patent and rights over it. Fortunately exists an alternative called cJTAG.
cJTAG is not well supported by open-source solutions like OpenOCD (the “support” it forcing the chip to fallback to 4 wires). Today I tested cJTAG using a J-Link Base probe on Linux and it worked fine.
I connected these pins from board to Segger J-Link:
NRST – RESET
TCK – TCK
TMS – TMS
GND – GND
3V – VTref
Then just executed:
$ sudo JLinkExe -if cjtag -device CC2640R2F [sudo] password for alan: SEGGER J-Link Commander V6.80d (Compiled Jun 26 2020 17:19:52) DLL version V6.80d, compiled Jun 26 2020 17:19:40 Connecting to J-Link via USB…Updating firmware: J-Link V11 compiled Jun 9 2020 13:38:27 Replacing firmware: J-Link V11 compiled Jan 7 2020 16:52:13 Waiting for new firmware to boot New firmware booted successfully O.K. Firmware: J-Link V11 compiled Jun 9 2020 13:38:27 Hardware version: V11.00 S/N: 51000000 License(s): GDB VTref=3.044V Type "connect" to establish a target connection, '?' for help J-Link>connect Device position in JTAG chain (IRPre,DRPre) : -1,-1 => Auto-detect JTAGConf> Specify target interface speed [kHz]. : 4000 kHz Speed> Device "CC2640R2F" selected. Connecting to target via cJTAG InitTarget: Found ICE-Pick with ID: 0xBB99A02F InitTarget: Can not find CPU TAP (IDCODE mismatch. Expected 0x00000477, found: 0xFFFFFFFF InitTarget: Found ICE-Pick with ID: 0xBB99A02F InitTarget: Found CPU TAP 0x4BA00477 Failed to power up DAP InitTarget: Found ICE-Pick with ID: 0xBB99A02F InitTarget: Can not find CPU TAP (IDCODE mismatch. Expected 0x00000477, found: 0x00000000 InitTarget: Found ICE-Pick with ID: 0xBB99A02F InitTarget: Found CPU TAP 0x4BA00477 Cannot determine DP version. Assuming DPv0 Scanning AP map to find all available APs AP: Stopped AP scan as end of AP map has been reached AP: AHB-AP (IDR: 0x24770011) Iterating through AP map to find AHB-AP to use AP: Core found AP: AHB-AP ROM base: 0xE00FF000 CPUID register: 0x412FC231. Implementer code: 0x41 (ARM) Found Cortex-M3 r2p1, Little endian. FPUnit: 6 code (BP) slots and 2 literal slots CoreSight components: ROMTbl @ E00FF000 ROMTbl: E000E000, CID: B105E00D, PID: 000BB000 SCS ROMTbl: E0001000, CID: B105E00D, PID: 003BB002 DWT ROMTbl: E0002000, CID: B105E00D, PID: 002BB003 FPB ROMTbl: E0000000, CID: B105E00D, PID: 003BB001 ITM ROMTbl: E0040000, CID: B105900D, PID: 003BB923 TPIU-Lite Cortex-M3 identified. J-Link> savebin fw.bin 0x00000000 0x20000 Opening binary file for writing... [fw.bin] Reading 131072 bytes from addr 0x00000000 into file... O.K. J-Link>