Month: July 2020

Just a resume of my experience with iMXRT1060-EVK

I was trying to run NuttX RTOS on iMXRT1060_EVK board (it has an
external 8MiB QSPI Flash), but because my JLink EDU is version V8 it
doesn’t supports Cortex-M7.

Using the DAPLink drag-and-drop I can copy small nuttx firmwares
(i.e.: up to 73KB worked), but when I compile NuttX to PROTECTED Mode
it doesn’t work. Because the kernel is at the beginning of the flash
and the userspace is at offset +2MB. Then during the copy it reports

Then I tried to use OpenOCD. I got it working for debugging, but it
doesn’t have support to flash the QSPI for NXP chips, only for

While searching for a solution I found this post:

“You can actually run the LPC-Link2 firmware on the onboard debug
probe of the RT1064-EVK board, in place of the default DAP-Link
firmware. For more details see:”

That points to this post:

Reading this PDF I discovered that if I wire the jumper J42 near the
LPC4322, the firmware will work as a native LPC-Link2, instead of a

It is strange because in the User’s Guide there is nothing about this

And in fact it works as DFU mode:

[ 638.833516] usb 1-1: new high-speed USB device number 9 using xhci_hcd
[ 638.982422] usb 1-1: New USB device found, idVendor=1fc9,
idProduct=000c, bcdDevice= 1.00
[ 638.982428] usb 1-1: New USB device strings: Mfr=1, Product=2, SerialNumber=3
[ 638.982434] usb 1-1: Product: LPC
[ 638.982436] usb 1-1: Manufacturer: NXP
[ 638.982439] usb 1-1: SerialNumber: ABCD
$ sudo dfu-util -d 0x1fc9:0x000c -l
dfu-util 0.9

Found DFU: [1fc9:000c] ver=0100, devnum=9, cfg=1, intf=0, path="1-1",
alt=0, name="DFU", serial="ABCD"

But I need to find the .hdr file to implement the LPCScrypt for this
iMXRT1060 chip, like I did some time ago for LPC43:

I have a LPCXpresso54628 board here, then I thought about the idea of
using its LPC-Link2 to program the iMXRT1060. But that should be more complicated.

JLinkExe Flash failing to STM32L496RE

Please specify device / core.
Type '?' for selection dialog
Specify target interface speed [kHz]. <Default>: 4000 kHz
Device "STM32L496RE" selected.

Connecting to target via SWD
Found SW-DP with ID 0x2BA01477
STM32 (Protection Detection): Unexpected IDCODE DEV_ID 0x 461 found. Only checking the 1st flash bank for write protection.
Found SW-DP with ID 0x2BA01477
Unknown DP version. Assuming DPv0
Scanning AP map to find all available APs
AP[1]: Stopped AP scan as end of AP map has been reached
AP[0]: AHB-AP (IDR: 0x24770011)
Iterating through AP map to find AHB-AP to use
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xE00FF000
CPUID register: 0x410FC241. Implementer code: 0x41 (ARM)
Found Cortex-M4 r0p1, Little endian.
FPUnit: 6 code (BP) slots and 2 literal slots
CoreSight components:
ROMTbl[0] @ E00FF000
ROMTbl[0][0]: E000E000, CID: B105E00D, PID: 000BB00C SCS-M7
ROMTbl[0][1]: E0001000, CID: B105E00D, PID: 003BB002 DWT
ROMTbl[0][2]: E0002000, CID: B105E00D, PID: 002BB003 FPB
ROMTbl[0][3]: E0000000, CID: B105E00D, PID: 003BB001 ITM
ROMTbl[0][4]: E0040000, CID: B105900D, PID: 000BB9A1 TPIU
ROMTbl[0][5]: E0041000, CID: B105900D, PID: 000BB925 ETM
Cortex-M4 identified.
J-Link>loadbin nuttx.bin, 0
Halting CPU for downloading file.
Downloading file [nuttx.bin]…
Writing target memory failed.
Erasing device…
J-Link: Flash download: Only internal flash banks will be erased.
To enable erasing of other flash banks like QSPI or CFI, it needs to be enabled via "exec EnableEraseAllFlashBanks"
Erasing flash [100%] Done.
Error: Failed to erase chip @ address 0x08000000 (Algo87: Unspecified error #1)
Failed to erase chip.
Failed to execute RAMCode for chip erase!
J-Link: Flash download: Total time needed: 0.105s (Prepare: 0.064s, Compare: 0.000s, Erase: 0.001s, Program: 0.000s, Verify: 0.000s, Restore: 0.038s)
ERROR: Erase returned with error code -5.

Strange, after resetting the board and writing a .hex instead of a .bin worked:

J-Link>loadbin nuttx.hex, 0
'loadbin': Performing implicit reset & halt of MCU.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via AIRCR.SYSRESETREQ.
Downloading file [nuttx.hex]…
J-Link: Flash download: Bank 0 @ 0x08000000: 1 range affected (251904 bytes)
J-Link: Flash download: Total: 2.972s (Prepare: 0.120s, Compare: 0.038s, Erase: 0.000s, Program & Verify: 2.749s, Restore: 0.063s)
J-Link: Flash download: Program & Verify speed: 89 KB/s

Creating a VIM macro to align variable definition on header files

I was looking for a way to align registers definitions like these:

#define REGISTER_XYZ 0x0001
#define REGISTER_A 0x0002

And I found this nice tip:

qa -- Record a macro in hotkey a
0 -- Go to the beginning of the line
f= -- Go to the first equals sign
100i <Esc> -- (There's a single space after the i, and the <Esc> means press escape, don't type "<Esc>".) Insert 100 spaces
8| -- Go to the 8th column (sorry, you'll have to manually figure out which column to align to)
dw -- Delete until the next non-space character
j -- Go to the next line
q -- Stop recording.

In my case I just replaced the “f=” with “f0” and “8|” with “33|”


Tips when booting with NSH

If you want to start your application on NuttX directly without using the NSH you can setup your “app_main” in the ENTRYPOINT, although you will see that some drivers will not start anymore.

You can fix it enabling the “Board Late Init” in the menuconfig:

RTOS Features ---> RTOS hooks ---> [*] Custom board late initialization

Also you need to disable the architecture-specific initialization:

Application Configuration ---> NSH Library ---> Have architecture-specific initialization