Some facts about Atmel SAM L21 microcontroller

The Atmel SAML21 microcontroller has a complex clock structure, in fact even more complex than some high end processors. This complexity brings more flexibility to enable individually each peripheral clock source.

The SAM L21 has nine Clocks Generator, each generator can select a specific clock input (XOSC, GCLK_IN, GCLK_GEN1, OSCULP32K, OSC32K, OSC16M, DFLL48M or DPLL96M). Exception is Generator1 (GCLK_GEN1) that cannot select GCLK_GEN1 (itself) because its clock output can be used as clock input by other Generators.

Each Generator has a internal prescaler to divide the input clock up to 128 (again CLK_GEN1 is exception because it can divide up to 32768). And the Generator output clock can be used by up to 64 Peripheral channels (in the SAML21 there are “only” 35 channels).

Basic Operation

-The GCLK module has 9 Generic Clock Generators

- Up to 64 Peripheral Channels and the Main Clock signal (GCLK_MAIN) can be sourced from Generator

- The clock source selected as input to a Generator can be used directly or prescaled

- The GCLK Module doesn't have a general enable/disable bit

- The GCLK Module can be reset by setting the Software Reset bit (CTRLA.SWRST)

  - All register from GCLK module will be reset, except Per.Channels and associated Generators

- All Generators can be set to run from 1 of 9 clock sources, except GCLK_GEN[1]
  - GCLK_GEN[1] can be used to supply clock for all others 8 Generators

- Each generator GCLK_GEN[x] can be connected to 1 pin (GCLK_IO[y])

- GCLK_GEN[0] is used as GCLK_MAIN

- Each Genarator can be enabled/disabled by setting Generator Enable bit (GENCTRLn.GENEN = 1/0).

- The clock for of each Generator can be selected by setting the Source Select bit (GENCTRL[n].SRC)

  - When changing of clock source the  register SYNCBUSY.GENCTRL_n will remain 1 until the source is fine

- The clock freq of each generator can be divided setting GENCTRLn.DIV
  - If GENCTRLn.DIVSEL = 0 and GENCTRLn.DIV is 0 or 1 the freq. is not divided

- If division factor is odd the Duty cycle will not be 50/50
  - Setting the Improve Duty Cycle (GENCTRLn.IDC) will result in a 50/50 duty cycle

- If Output Enable (GENCTRLn.OE = 1) and GENCTRLn.GENEN = 1 the clock is outputed to GCLK_IO pin

Peripheral Clock

- Before enabling a Peripheral channel the Generator clock needs to be enabled (GENCTRLn.GEN = 1) and
this Generator is already selected as source for the Peripheral Channel (PCHCTRLm.GEN)

- The Peripheral Channel is enabled in the Channel Enable bit (PCHCTRLm.CHEN = 1)

- The Peripheral Channel's Generator (PCHCTRLm.GEN) needs to be set with Channel disabled (PCHCTRLm.CHEN = 0)

- The Peripheral clock configuration can be locked setting Write Lock bit (PCHCTRLm.WRTLOCK=1)

  - When WRTLOCK is set the Generator will be locked, exception is Generator 0 that is sorce of GCLK_MAIN

- In SAM L21 we have 35 Peripheral channels (index 0 up to 34)